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PIC18F2220/2320/4220/4320 Data Sheet
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
2003 Microchip Technology Inc.
DS39599C
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS39599C-page ii
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28/40/44-Pin High-Performance, Enhanced Flash MCUs with 10-bit A/D and nanoWatt Technology
Low-Power Features:
* Power Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off * Power Consumption modes: - PRI_RUN: 150 A, 1 MHz, 2V - PRI_IDLE: 37 A, 1 MHz, 2V - SEC_RUN: 14 A, 32 kHz, 2V - SEC_IDLE: 5.8 A, 32 kHz, 2V - RC_RUN: 110 A, 1 MHz, 2V - RC_IDLE: 52 A, 1 MHz, 2V - Sleep: 0.1 A, 1 MHz, 2V * Timer1 Oscillator: 1.1 A, 32 kHz, 2V * Watchdog Timer: 2.1 A * Two-Speed Oscillator Start-up
Peripheral Highlights:
* High current sink/source 25 mA/25 mA * Three external interrupts * Up to 2 Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution is 6.25 ns (TCY/16) - Compare is 16-bit, max. resolution is 100 ns (TCY) - PWM output: PWM resolution is 1 to 10-bit * Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead-time - Auto-Shutdown and Auto-Restart * Compatible 10-bit, up to 13-channel Analog-to-Digital Converter module (A/D) with programmable acquisition time * Dual analog comparators * Addressable USART module: - RS-232 operation using internal oscillator block (no external crystal required)
Oscillators:
* Four Crystal modes: - LP, XT, HS: up to 25 MHz - HSPLL: 4-10 MHz (16-40 MHz internal) * Two External RC modes, up to 4 MHz * Two External Clock modes, up to 40 MHz * Internal oscillator block: - 8 user selectable frequencies: 31 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz - 125 kHz-8 MHz calibrated to 1% - Two modes select one or two I/O pins - OSCTUNE - Allows user to shift frequency * Secondary oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
* 100,000 erase/write cycle Enhanced Flash program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * Flash/Data EEPROM Retention: > 40 years * Self-programmable under software control * Priority levels for interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s - 2% stability over VDD and Temperature * Single-supply 5V In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Wide operating voltage range: 2.0V to 5.5V
MSSP I/O CCP/ 10-bit ECCP A/D (ch) (PWM) 10 10 13 13 2/0 2/0 1/1 1/1 SPITM Y Y Y Y Master USART I2CTM Y Y Y Y Y Y Y Y Comparators 2 2 2 2
Program Memory Device
Data Memory
Flash # Single Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) 4096 8192 4096 8192 2048 4096 2048 4096 512 512 512 512 256 256 256 256
Timers 8/16-bit
PIC18F2220 PIC18F2320 PIC18F4220 PIC18F4320
25 25 36 36
2/3 2/3 2/3 2/3
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DS39599C-page 1
PIC18F2220/2320/4220/4320
Pin Diagrams
PDIP
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
SPDIP, SOIC
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing. Note: Pin compatible with 40-pin PIC16C7X devices.
PIC18F2220 PIC18F2320
PIC18F4220 PIC18F4320
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2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Pin Diagrams (Cont.'d)
TQFP
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2* NC 44 43 42 41 40 39 38 37 36 35 34
* RB3 is the alternate pin for the CCP2 pin multiplexing.
QFN
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2* RC0/T1OSO/T1CKI
NC NC RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2*
1 2 3 4 5 6 7 8 9 10 11
PIC18F4220 PIC18F4320
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT
* RB3 is the alternate pin for the CCP2 pin multiplexing.
2003 Microchip Technology Inc.
RB3/AN9/CCP2* NC RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2
1 2 3 4 5 6 7 8 9 10 11
PIC18F4220 PIC18F4320
33 32 31 30 29 28 27 26 25 24 23
OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VSS VDD NC RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT
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PIC18F2220/2320/4220/4320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 19 3.0 Power Managed Modes ............................................................................................................................................................. 29 4.0 Reset .......................................................................................................................................................................................... 43 5.0 Memory Organization ................................................................................................................................................................. 53 6.0 Flash Program Memory .............................................................................................................................................................. 71 7.0 Data EEPROM Memory ............................................................................................................................................................. 81 8.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 85 9.0 Interrupts .................................................................................................................................................................................... 87 10.0 I/O Ports ................................................................................................................................................................................... 101 11.0 Timer0 Module ......................................................................................................................................................................... 117 12.0 Timer1 Module ......................................................................................................................................................................... 121 13.0 Timer2 Module ......................................................................................................................................................................... 127 14.0 Timer3 Module ......................................................................................................................................................................... 129 15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 133 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 141 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 155 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 195 19.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 211 20.0 Comparator Module.................................................................................................................................................................. 221 21.0 Comparator Voltage Reference Module ................................................................................................................................... 227 22.0 Low-Voltage Detect .................................................................................................................................................................. 231 23.0 Special Features of the CPU .................................................................................................................................................... 237 24.0 Instruction Set Summary .......................................................................................................................................................... 255 25.0 Development Support............................................................................................................................................................... 299 26.0 Electrical Characteristics .......................................................................................................................................................... 305 27.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 343 28.0 Packaging Information.............................................................................................................................................................. 361 Appendix A: Revision History............................................................................................................................................................. 369 Appendix B: Device Differences......................................................................................................................................................... 369 Appendix C: Conversion Considerations ........................................................................................................................................... 370 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 370 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 371 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 371 Index .................................................................................................................................................................................................. 373 On-Line Support................................................................................................................................................................................. 383 Systems Information and Upgrade Hot Line ...................................................................................................................................... 383 Reader Response .............................................................................................................................................................................. 384 PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 385
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2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2003 Microchip Technology Inc.
DS39599C-page 5
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 6
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
1.0 DEVICE OVERVIEW
This document contains device specific information for the following devices: * PIC18F2220 * PIC18F4220 * PIC18F2320 * PIC18F4320 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price with the addition of highendurance Enhanced Flash program memory. On top of these features, the PIC18F2220/2320/4220/4320 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation.
1.1
1.1.1
New Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F2220/2320/4220/4320 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-fly Mode Switching: The power managed modes are invoked by user code during operation, allowing the user to incorporate power saving ideas into their application's software design. * Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.8 and 2.2 A, respectively.
1.2
Other Special Features
1.1.2
MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F2220/2320/4220/4320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input with the second pin reassigned as general I/O). * Two External RC Oscillator modes with the same pin options as the External Clock modes. * An internal oscillator block, which provides a 31 kHz INTRC clock and an 8 MHz clock with 6 program selectable divider ratios (4 MHz to 125 kHz) for a total of 8 clock frequencies.
* Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto-Shutdown for disabling PWM outputs on interrupt or other select conditions and Auto-Restart to reactivate outputs once the condition has cleared. * Addressable USART: This serial communication module is capable of standard RS-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. * 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature.
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PIC18F2220/2320/4220/4320
1.3 Details on Individual Family Members
3. I/O ports (3 bidirectional ports and 1 input only port on PIC18F2X20 devices, 5 bidirectional ports on PIC18F4X20 devices) CCP and Enhanced CCP implementation (PIC18F2X20 devices have 2 standard CCP modules, PIC18F4X20 devices have one standard CCP module and one ECCP module) Parallel Slave Port (present only on PIC18F4X20 devices)
Devices in the PIC18F2220/2320/4220/4320 family are available in 28-pin (PIC18F2X20) and 40/44-pin (PIC18F4X20) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. 2. Flash program memory (4 Kbytes for PIC18FX220 devices, 8 Kbytes for PIC18FX320) A/D channels (10 for PIC18F2X20 devices, 13 for PIC18F4X20 devices)
4.
5.
All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3.
TABLE 1-1:
DEVICE FEATURES
PIC18F2220 DC - 40 MHz 4096 2048 512 256 19 Ports A, B, C (E) 4 2 0 MSSP, Addressable USART No 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions 28-pin SPDIP 28-pin SOIC PIC18F2320 DC - 40 MHz 8192 4096 512 256 19 Ports A, B, C (E) 4 2 0 MSSP, Addressable USART No 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions 28-pin SPDIP 28-pin SOIC PIC18F4220 DC - 40 MHz 4096 2048 512 256 20 4 1 1 MSSP, Addressable USART Yes 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions 40-pin PDIP 44-pin TQFP 44-pin QFN PIC18F4320 DC - 40 MHz 8192 4096 512 256 20 4 1 1 MSSP, Addressable USART Yes 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions 40-pin PDIP 44-pin TQFP 44-pin QFN
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications
Ports A, B, C, D, E Ports A, B, C, D, E
Parallel Communications (PSP) 10-bit Analog-to-Digital Module Resets (and Delays)
Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages
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2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 1-1: PIC18F2220/2320 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2> 21 21 Address Latch Program Memory (4 Kbytes) Data Latch 20 inc/dec logic
8
8
8
8
Data Latch Data RAM (512 Bytes) Address Latch
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC2/CLKO/RA6(3) OSC1/CLKI/RA7(3) PORTB RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2(1) RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8
PCLATU PCLATH PCU PCH PCL Program Counter
12(2) Address<12> 4 BSR 12 4 FSR0 Bank0, F FSR1 FSR2 12
31 Level Stack
16 Table Latch 8 ROM Latch Decode
inc/dec logic
Instruction Register Instruction Decode & Control 3 8 PRODH PRODL 8 x 8 Multiply
OSC1(3) OSC2(3) T1OSI T1OSO
Internal Oscillator Block INT RC Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer
BIT OP 8
WREG 8 8 ALU<8>
8
PORTE 8 Precision Voltage Reference RE3(2)
MCLR(2) VDD, VSS
Low-Voltage Programming In-Circuit Debugger
Brown-out Reset Fail-Safe Clock Monitor
Timer0 (8- or 16-bit)
Timer1 (16-bit)
Timer2 (8-bit)
Timer3 (16-bit)
10-bit A/D Converter
CCP1
CCP2
Master Synchronous Serial Port
Addressable USART
Data EEPROM (256 Bytes)
Note
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 configuration bit. 2: RE3 is available only when the MCLR Resets are disabled. 3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information.
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DS39599C-page 9
PIC18F2220/2320/4220/4320
FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM
Data Bus<8> PORTA 21 Table Pointer <2> 21 21 Address Latch Program Memory (8 Kbytes) Data Latch 31 Level Stack 20 PCLATU PCLATH PCU PCH PCL Program Counter inc/dec logic 8 8 8 8 Data Latch Data RAM (512 Bytes) Address Latch 12(2) Address<12> 4 BSR 12 4 FSR0 Bank0, F FSR1 FSR2 12 PORTB RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2(1) RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 OSC1(3) OSC2(3) T1OSI T1OSO Internal Oscillator Block INT RC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Low-Voltage Programming In-Circuit Debugger Brown-out Reset Fail-Safe Clock Monitor Precision Voltage Reference BIT OP 8 WREG 8 8 ALU<8> 8 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS RE3(2) 8 PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC2/CLKO/RA6(3) OSC1/CLKI/RA7(3)
16 Table Latch 8 ROM Latch Decode
inc/dec logic
Instruction Register Instruction Decode & Control 3 8 PRODH PRODL 8 x 8 Multiply
MCLR(2) VDD, VSS
Timer0 (8- or 16-bit)
Timer1 (16-bit)
Timer2 (8-bit)
Timer3 (16-bit)
10-bit A/D Converter
Enhanced CCP
CCP2
Master Synchronous Serial Port
Addressable USART
Data EEPROM (256 Bytes)
Note
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit. 2: RE3 is available only when the MCLR Resets are disabled. 3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information.
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PIC18F2220/2320/4220/4320
TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS
Pin Number Pin Buffer PDIP SOIC Type Type 1 1 I P I 9 9 I I I/O 10 10 O O I/O 2 2 I/O I 3 3 I/O I 4 4 I/O I I O 5 5 I/O I I 6 6 I/O I O 7 7 I/O I I I O TTL Analog TTL Analog -- Digital I/O. Analog input 4. SPI Slave Select input. Low-Voltage Detect input. Comparator 2 output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. ST/OD ST -- Digital I/O. Open-drain when configured as output. Timer0 external clock input. Comparator 1 output. TTL Analog Analog Digital I/O. Analog input 3. A/D Reference Voltage (High) input. TTL Analog Analog Analog Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. Comparator Reference Voltage output. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. -- -- TTL ST Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Pin Name MCLR/VPP/RE3 MCLR VPP RE3 OSC1/CLKI/RA7 OSC1 CLKI RA7 OSC2/CLKO/RA6 OSC2 CLKO RA6 RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/LVDIN/C2OUT RA5 AN4 SS LVDIN C2OUT RA6 RA7
ST ST
Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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PIC18F2220/2320/4220/4320
TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer PDIP SOIC Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0 RB0 AN12 INT0 RB1/AN10/INT1 RB1 AN10 INT1 RB2/AN8/INT2 RB2 AN8 INT2 RB3/AN9/CCP2 RB3 AN9 CCP2(1) RB4/AN11/KBI0 RB4 AN11 KBI0 RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD 21 21 I/O I I 22 22 I/O I I 23 23 I/O I I 24 24 I/O I I/O 25 25 I/O I I 26 26 I/O I I/O 27 27 I/O I I/O 28 28 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-voltage ICSP programming enable pin. TTL Analog TTL Digital I/O. Analog input 11. Interrupt-on-change pin. TTL Analog ST Digital I/O. Analog input 9. Capture2 input, Compare2 output, PWM2 output. TTL Analog ST Digital I/O. Analog input 8. External interrupt 2. TTL Analog ST Digital I/O. Analog input 10. External interrupt 1. TTL Analog ST Digital I/O. Analog input 12. External interrupt 0. Pin Name
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer PDIP SOIC Type Type 11 11 I/O O I 12 12 I/O I I/O 13 13 I/O I/O O 14 14 I/O I/O I/O 15 15 I/O I I/O 16 16 I/O O 17 17 I/O O I/O 18 18 I/O I I/O -- 20 -- 20 -- P P 8, 19 8, 19 ST ST ST -- -- -- Digital I/O. USART asynchronous receive. USART synchronous data (see related TX/CK). See MCLR/VPP/RE3 pin. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. ST -- ST Digital I/O. USART asynchronous transmit. USART synchronous clock (see related RX/DT). ST -- Digital I/O. SPI data out. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST -- Digital I/O. Capture1 input/Compare1 output/PWM1 output. Enhanced CCP1 output. ST CMOS ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) RC2/CCP1/P1A RC2 CCP1 P1A RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT RE3 VSS VDD Pin Name
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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TABLE 1-3:
Pin Name MCLR/VPP/RE3 MCLR VPP RE3 OSC1/CLKI/RA7 OSC1 CLKI 13 30 32 I I
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS
Pin Buffer PDIP TQFP QFN Type Type 1 18 18 I P I ST Pin Number Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.
ST ST
RA7 OSC2/CLKO/RA6 OSC2 CLKO RA6 RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/LVDIN/ C2OUT RA5 AN4 SS LVDIN C2OUT RA6 RA7 2 19 19 14 31 33
I/O O O I/O
Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. TTL -- -- TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port.
I/O I 3 20 20 I/O I 4 21 21 I/O I I O 5 22 22 I/O I I 6 23 23 I/O I O 7 24 24 I/O I I I O
TTL Analog TTL Analog TTL Analog Analog Analog TTL Analog Analog ST/OD ST --
Digital I/O. Analog input 0. Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator reference voltage output. Digital I/O. Analog input 3. A/D reference voltage (High) input. Digital I/O. Open-drain when configured as output. Timer0 external clock input. Comparator 1 output.
TTL Analog TTL Analog --
Digital I/O. Analog input 4. SPI slave select input. Low-Voltage Detect input. Comparator 2 output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer PDIP TQFP QFN Type Type Pin Number Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0 RB0 AN12 INT0 RB1/AN10/INT1 RB1 AN10 INT1 RB2/AN8/INT2 RB2 AN8 INT2 RB3/AN9/CCP2 RB3 AN9 CCP2(1) RB4/AN11/KBI0 RB4 AN11 KBI0 RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD
33
8
9 I/O I I TTL Analog ST TTL Analog ST TTL Analog ST TTL Analog ST TTL Analog TTL TTL TTL ST TTL TTL ST TTL TTL ST Digital I/O. Analog input 12. External interrupt 0. Digital I/O. Analog input 10. External interrupt 1. Digital I/O. Analog input 8. External interrupt 2. Digital I/O. Analog input 9. Capture2 input, Compare2 output, PWM2 output. Digital I/O. Analog input 11. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Low-voltage ICSP programming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.
34
9
10 I/O I I
35
10
11 I/O I I
36
11
12 I/O I I/O
37
14
14 I/O I I
38
15
15 I/O I I/O
39
16
16 I/O I I/O
40
17
17 I/O I I/O
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer PDIP TQFP QFN Type Type 15 32 34 I/O O I 16 35 35 I/O I I/O 17 36 36 I/O I/O O 18 37 37 I/O I/O I/O 23 42 42 I/O I I/O 24 43 43 I/O O 25 44 44 I/O O I/O 26 1 1 I/O I I/O ST ST ST Digital I/O. USART asynchronous receive. USART synchronous data (see related TX/CK). ST -- ST Digital I/O. USART asynchronous transmit. USART synchronous clock (see related RX/DT). ST -- Digital I/O. SPI data out. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST -- Digital I/O. Capture1 input/Compare1 output/PWM1 output. Enhanced CCP1 output. ST CMOS ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Pin Number Description PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) RC2/CCP1/P1A RC2 CCP1 P1A RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer PDIP TQFP QFN Type Type Pin Number Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5/P1B RD5 PSP5 P1B RD6/PSP6/P1C RD6 PSP6 P1C RD7/PSP7/P1D RD7 PSP7 P1D
19
38
38 I/O I/O ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL -- ST TTL -- ST TTL -- Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output.
20
39
39 I/O I/O
21
40
40 I/O I/O
22
41
41 I/O I/O
27
2
2 I/O I/O
28
3
3 I/O I/O O
29
4
4 I/O I/O O
30
5
5 I/O I/O O
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer PDIP TQFP QFN Type Type Pin Number Description PORTE is a bidirectional I/O port.
RE0/AN5/RD RE0 AN5 RD RE1/AN6/WR RE1 AN6 WR RE2/AN7/CS RE2 AN7 CS RE3 VSS VDD NC
8
25
25 I/O I I ST Analog TTL Digital I/O. Analog input 5. Read control for Parallel Slave Port (see also WR and CS pins). Digital I/O. Analog input 6. Write control for Parallel Slave Port (see CS and RD pins). Digital I/O. Analog input 7. Chip select control for Parallel Slave Port (see related RD and WR). See MCLR/VPP/RE3 pin. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. No connect.
9
26
26 I/O I I ST Analog TTL
10
27
27 I/O I I ST Analog TTL -- -- -- NC
1 12, 31
18
18
-- P P NC
6, 29 6, 30, 31 7, 8, 28, 29 13
11, 32 7, 28 -- --
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no diode to VDD) Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared.
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2.0
2.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 2-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)
OSC1 To Internal Logic Sleep
The PIC18F2X20 and PIC18F4X20 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. 5. 6. 7. 8. LP XT HS HSPLL RC RCIO INTIO1 INTIO2 Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with FOSC/4 output External Clock with I/O on RA6
C1(1)
XTAL RS(2) C2(1) Note 1: 2: 3: OSC2
RF(3)
PIC18FXXXX
See Table 2-1 and Table 2-2 for initial values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Typical Capacitor Values Used: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 56 pF 47 pF 33 pF 27 pF 22 pF OSC2 56 pF 47 pF 33 pF 27 pF 22 pF
9. EC 10. ECIO
2.2
Crystal Oscillator/Ceramic Resonators
HS
In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes on page 20 for additional information. Resonators Used: 455 kHz 2.0 MHz 16.0 MHz 4.0 MHz 8.0 MHz
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PIC18F2220/2320/4220/4320
TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz XT HS 1 MHz 4 MHz 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 LP 33 pF 15 pF 33 pF 27 pF 27 pF 22 pF 15 pF C2 33 pF 15 pF 33 pF 27 pF 27 pF 22 pF 15 pF
Clock from Ext. System Open OSC1
An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2:
Osc Type
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
PIC18FXXXX
OSC2 (HS Mode)
2.3
HSPLL
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz
A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled.
FIGURE 2-3:
Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: RS may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
PLL BLOCK DIAGRAM
HS Osc Enable PLL Enable (from Configuration Register 1H) OSC2
HS Mode OSC1 Crystal Osc
FIN FOUT
Phase Comparator
Loop Filter
/4
VCO MUX
SYSCLK
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PIC18F2220/2320/4220/4320
2.4 External Clock Input 2.5 RC Oscillator
The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)
OSC1/CLKI
Clock from Ext. System FOSC/4
PIC18FXXXX
OSC2/CLKO
FIGURE 2-6:
VDD REXT
RC OSCILLATOR MODE
The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode.
OSC1 CEXT
Internal Clock
FIGURE 2-5:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI
VSS FOSC/4 OSC2/CLKO
PIC18FXXXX
Recommended values: 3 k REXT 100 k CEXT > 20 pF Clock from Ext. System RA6
PIC18FXXXX
I/O (OSC2)
The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).
FIGURE 2-7:
VDD REXT
RCIO OSCILLATOR MODE
OSC1 CEXT VSS RA6 I/O (OSC2)
Internal Clock
PIC18FXXXX
Recommended values: 3 k REXT 100 k CEXT > 20 pF
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PIC18F2220/2320/4220/4320
2.6 Internal Oscillator Block
2.6.2 INTRC OUTPUT FREQUENCY
The PIC18F2X20/4X20 devices include an internal oscillator block which generates two different clock signals. Either can be used as the system's clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source which can be used to directly drive the system clock. It also drives a postscaler which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC) which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source or when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. Once set during factory calibration, the INTRC frequency will remain within 1% as temperature and VDD change across their full specified operating ranges.
2.6.3
OSCTUNE REGISTER
The internal oscillator's output has been calibrated at the factory but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.
These features are discussed in greater detail in Section 23.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 26).
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
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PIC18F2220/2320/4220/4320
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- bit 7 bit 7-6 bit 5-0 Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency (+12.5%, approximately) * * * * 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 * * * * 100000 = Minimum frequency (-12.5%, approximately) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
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PIC18F2220/2320/4220/4320
2.7 Clock Sources and Oscillator Switching
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several aspects of the system clock's operation, both in full power operation and in power managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power managed mode of operation. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator's output. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the system clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the system clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in secondary clock modes. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The IDLEN bit controls the selective shutdown of the controller's CPU in power managed modes. The use of these bits is discussed in more detail in Section 3.0 "Power Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to set the SCS0 bit will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts.
Like previous PIC18 devices, the PIC18F2X20 and PIC18F4X20 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2X20/4X20 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power managed operating modes. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power managed mode. PIC18F2X20/4X20 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T1CKI and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.2 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2X20/4X20 devices are shown in Figure 2-8. See Section 12.0 "Timer1 Module" for further details of the Timer1 oscillator. See Section 23.1 "Configuration Bits" for Configuration register details.
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FIGURE 2-8: PIC18F2X20/4X20 CLOCK DIAGRAM
Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator Block 8 MHz (INTOSC)
PIC18F2X20/4X20
4 x PLL
CONFIG1H <3:0> HSPLL LP, XT, HS, RC, EC
Clock Control
OSCCON<1:0>
Clock Source Option for Other Modules OSCCON<6:4> 8 MHz 4 MHz 110 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz 31 kHz 011 010 001 000 MUX 1 MHz 111 Internal Oscillator
T1OSI
MUX
T1OSC
Peripherals
CPU
IDLEN
INTRC Source
WDT, FSCM
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REGISTER 2-2: OSCCON REGISTER
R/W-0 IDLEN bit 7 bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power managed modes 0 = Run mode enabled; CPU core is clocked in power managed modes IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator start-up time-out timer has expired; primary oscillator is running 0 = Oscillator start-up time-out timer is running; primary oscillator is not ready IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes)(2) 00 = Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of IESO bit in Configuration Register 1H. 2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS R-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0
bit 6-4
bit 3
bit 2
bit 1-0
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2.7.2 OSCILLATOR TRANSITIONS
The PIC18F2X20/4X20 devices contain circuitry to prevent clocking "glitches" when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power Managed Modes". If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a system clock source (i.e., SSP slave, PSP, INTn pins, A/D conversions and others).
2.8
Effects of Power Managed Modes on the Various Clock Sources
2.9
Power-up Delays
When the device executes a SLEEP instruction, the system is switched to one of the power managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 "Power Managed Modes" for details. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power managed mode (see Section 23.2 "Watchdog Timer (WDT)" through Section 23.4 "Fail-Safe Clock Monitor"). The INTOSC output at 8 MHz may be used directly to clock the system or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output.
Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.1 "Power-on Reset (POR)" through Section 4.5 "Brown-out Reset (BOR)". The first timer is the Power-up Timer (PWRT) which provides a fixed delay on power-up (parameter 33, Table 26-10), if enabled, in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of 5 to 10 s, following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source.
TABLE 2-3:
RC, INTIO1 RCIO, INTIO2 ECIO EC LP, XT, and HS Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating, external resistor should pull high Floating, external resistor should pull high Floating, pulled by external clock Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level
OSC Mode
See Table 4-1 in Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset.
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NOTES:
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3.0 POWER MANAGED MODES
The PIC18F2X20 and PIC18F4X20 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These operating modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power managed modes: * Sleep mode * Idle modes * Run modes These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or INTOSC multiplexer); the Sleep mode does not use a clock source. The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator) and the Sleep mode offered by all PICmicro(R) devices (where all system clocks are stopped) are both offered in the PIC18F2X20/4X20 devices (SEC_RUN and Sleep modes, respectively). However, additional power managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The power managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. For PIC18F2X20/4X20 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset, or a WDT time-out (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power managed Run modes may also exit to Sleep mode or their corresponding Idle mode.
3.1
Selecting Power Managed Modes
Selecting a power managed mode requires deciding if the CPU is to be clocked or not and selecting a clock source. The IDLEN bit controls CPU clocking while the SC1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1.
3.1.1
CLOCK SOURCES
The clock source is selected by setting the SCS bits of the OSCCON register. Three clock sources are available for use in power managed Idle modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The secondary and internal oscillator block sources are available for the power managed modes (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source).
TABLE 3-1:
Mode
POWER MANAGED MODES
OSCCON Bits IDLEN <7> 0 0 0 0 1 1 1 SCS1:SCS0 <1:0> 00 00 01 1x 00 01 1x Module Clocking Available Clock and Oscillator Source CPU Off Clocked Clocked Clocked Off Off Off Peripherals Off Clocked Clocked Clocked Clocked Clocked Clocked None - All clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC, INTRC(1). This is the normal full power execution mode. Secondary - Timer1 Oscillator Internal Oscillator Block(1) Primary - LP, XT, HS, HSPLL, RC, EC Secondary - Timer1 Oscillator Internal Oscillator Block(1)
Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1:
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
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3.1.2 ENTERING POWER MANAGED MODES
In general, entry, exit and switching between power managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator) and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the power managed mode is triggered by the execution of a SLEEP instruction. Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between eight and nine clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register and T1RUN in the T1CON register. Only one of these bits will be set while in a power managed mode other than PRI_RUN. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering a power managed RC mode (same frequency) would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode; executing a SLEEP instruction is simply a trigger to place the controller into a power managed mode selected by the OSCCON register, one of which is Sleep mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new power managed mode specified by the new bit settings.
3.1.4
COMPARISONS BETWEEN RUN AND IDLE MODES
Clock source selection for the Run modes is identical to the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur. In Idle modes, the CPU is not clocked and is not running. In Run modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In Idle modes, a WDT time-out results in a wake from power managed modes. In Run modes, a WDT time-out results in a WDT Reset (see Table 3-2). During a wake-up from an Idle mode, the CPU starts executing code by entering the corresponding Run mode until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode).
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TABLE 3-2:
Power Managed Mode Sleep
COMPARISON BETWEEN POWER MANAGED MODES
CPU is clocked by ... WDT time-out causes a ... Peripherals are clocked by ... Not clocked Clock during wake-up (while primary becomes ready) None or INTOSC multiplexer if Two-Speed Start-up or Fail-Safe Clock Monitor are enabled.
Not clocked (not running) Wake-up
Any Idle mode
Not clocked (not running) Wake-up
Primary, Secondary or Unchanged from Idle mode INTOSC multiplexer (CPU operates as in corresponding Run mode). Secondary or INTOSC Unchanged from Run mode. multiplexer
Any Run mode
Secondary or INTOSC multiplexer
Reset
3.2
Sleep Mode
The power managed Sleep mode in the PIC18F2X20/ 4X20 devices is identical to that offered in all other PICmicro controllers. It is entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1). When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 23.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the system clocks. The IDLEN and SCS bits are not affected by the wake-up.
There is one exception to how the IDLEN bit functions. When all the low-power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters Sleep mode upon the execution of the SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PICmicro devices that do not offer power managed modes. If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake-up event occurs, CPU execution is delayed approximately 10 s while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the power managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready - this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to full power operation.
3.3
Idle Modes
The IDLEN bit allows the controller's CPU to be selectively shut down while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit.
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FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2
FIGURE 3-2:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 PC + 8 TOST(1) TPLL(1)
Wake-up Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle modes in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). When a wake-up event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 s is required between the wake-up event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1 Q2 Q3 Q4
OSC1 CPU Start-up Delay CPU Clock Peripheral Clock Program Counter PC PC + 2
Wake-up Event
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3.3.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the IDLEN bit, modifying to SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched to the Timer1 oscillator (see Figure 3-5), the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when trying to set the SCS0 bit (OSCCON<0>), the write to SCS0 will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. When a wake-up event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 s delay following the wake-up event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
FIGURE 3-5:
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter 1 2 3 4 5 6 Clock Transition 7 8
PC
PC + 2
FIGURE 3-6:
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI OSC1 TOST(1) PLL Clock Output TPLL(1) 1 2 3456 Clock Transition 7 8
CPU Clock Peripheral Clock Program Counter PC PC + 2 OSTS bit Set PC + 4 PC + 6
Wake-up from Interrupt Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.3.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to a non-zero value (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. When a wake-up event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 s delay following the wake-up event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 1 2 3 4 5 6 7 8
Clock Transition
FIGURE 3-8:
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC Multiplexer OSC1 TOST(1) PLL Clock Output TPLL(1) 1 2 3456 Clock Transition 7 8
CPU Clock Peripheral Clock Program Counter PC PC + 2 OSTS bit Set PC + 4 PC + 6
Wake-up from Interrupt Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.4 Run Modes
If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock. Wake-up from a power managed Run mode can be triggered by an interrupt, or any Reset, to return to full power operation. As the CPU is executing code in Run modes, several additional exits from Run modes are possible. They include exit to Sleep mode, exit to a corresponding Idle mode, and exit by executing a RESET instruction. While the device is in any of the power managed Run modes, a WDT time-out will result in a WDT Reset. SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when trying to set the SCS0 bit, the write to SCS0 will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result.
3.4.1
PRI_RUN MODE
The PRI_RUN mode is the normal full power execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power managed modes). All other power managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur. There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 "Oscillator Control Register").
When a wake-up event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up.
3.4.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source.
FIGURE 3-9:
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q2 1 2 3 4 5 6 Clock Transition 7 8 Q3 Q4 Q1 Q2 Q3
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter
PC
PC + 2
PC + 2
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3.4.3 RC_RUN MODE
Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to, and exit from, RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer. Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.
If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks. If the IRCF bits are changed from all clear (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes in approximately 1 ms. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. When a wake-up event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-10:
TIMING TRANSITION TO RC_RUN MODE
Q1 1 2 3 4 5 6 7 8 Q2 Q3 Q4 Q1 Q2 Q3
Q4 Q1 Q2 Q3 Q4 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC
Clock Transition
PC + 2
PC + 4
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3.4.4 EXIT TO IDLE MODE
3.5
An exit from a power managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source.
Wake-up From Power Managed Modes
An exit from any of the power managed modes is triggered by an interrupt, a Reset, or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Section 3.2 "Sleep Mode" through Section 3.4 "Run Modes"). Note: If application code is timing sensitive, it should wait for the OSTS bit to become set before continuing. Use the interval during the low-power exit sequence (before OSTS is set) to perform timing insensitive "housekeeping" tasks.
3.4.5
EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke Sleep mode from the normal operating (full power) mode. The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled, in the T1CON register. All clock source status bits are cleared (OSTS, IOFS and T1RUN).
Device behavior during Low-Power mode exits is summarized in Table 3-3.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the device to exit a power managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Lower Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 "Interrupts").
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TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES)
Primary System Clock Power Managed Mode Exit Delay Clock Ready Status Bit (OSCCON) OSTS 5-10 s(5) -- IOFS OST OST + 2 ms 5-10 s(5) 1 ms
(4) (2)
Clock in Power Managed Mode
Activity During Wake-up from Power Managed Mode Exit by Interrupt Exit by Reset
LP, XT, HS Primary System HSPLL Clock (1) (PRI_IDLE mode) EC, RC, INTRC INTOSC(2) LP, XT, HS T1OSC or INTRC(1) HSPLL EC, RC, INTRC(1) INTOSC HSPLL EC, RC, INTRC(1) INTOSC HSPLL EC, RC, INTRC(1) INTOSC Note 1: 2: 3: 4: 5:
(2) (2)
CPU and peripherals Not clocked or clocked by primary clock Two-Speed Start-up and executing (if enabled)(3). instructions. CPU and peripherals clocked by selected power managed mode clock and executing instructions until primary clock source becomes ready.
OSTS -- IOFS OSTS -- IOFS OSTS -- IOFS
LP, XT, HS INTOSC(2)
OST OST + 2 ms 5-10 s(5) None OST OST + 2 ms 5-10 s(5) 1 ms(4)
LP, XT, HS Sleep mode
Not clocked or Two-Speed Start-up (if enabled) until primary clock source becomes ready(3).
In this instance, refers specifically to the INTRC clock source. Includes both the INTOSC 8 MHz source and postscaler derived frequencies. Two-Speed Start-up is covered in greater detail in Section 23.3 "Two-Speed Start-up". Execution continues during the INTOSC stabilization period. Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 "Idle Modes").
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3.5.2 EXIT BY RESET 3.5.4
Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 23.4 "Fail-Safe Clock Monitor") are enabled in Configuration Register 1H, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all Resets, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.
EXIT WITHOUT AN OSCILLATOR START-UP DELAY
Certain exits from power managed modes do not invoke the OST at all. These are: * PRI_IDLE mode, where the primary clock source is not stopped; and * the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay (approximately 10 s) following the wake-up event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
3.6
INTOSC Frequency Drift
3.5.3
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending on which power managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in a wake-up from the power managed mode (see Section 3.2 "Sleep Mode" through Section 3.4 "Run Modes"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 23.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source.
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer and the RC_RUN/RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples are shown but other techniques may be used.
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3.6.1 EXAMPLE - USART 3.6.3
An adjustment may be indicated when the USART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high - try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low - increment OSCTUNE.
EXAMPLE - CCP IN CAPTURE MODE
3.6.2
EXAMPLE - TIMERS
This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast - decrement OSCTUNE.
A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast - decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow - increment OSCTUNE.
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NOTES:
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4.0 RESET
The PIC18F2X20/4X20 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset while executing instructions MCLR Reset when not executing instructions Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table 4-2. These bits are used in software to determine the nature of the Reset. See Table 4-3 for a full description of the Reset states of all registers. A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. The enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>). See Section 23.1 "Configuration Bits" for more information.
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred.
FIGURE 4-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOREN OST/PWRT 1024 Cycles OST 10-bit Ripple Counter OSC1 32 s INTRC(1) Chip_Reset R Q S POR Pulse
PWRT
65.5 ms
11-bit Ripple Counter
Enable PWRT Enable OST(2) Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations.
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4.1 Power-on Reset (POR) 4.3 Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power managed modes.
4.4
PLL Lock Time-out
FIGURE 4-2:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out.
VDD D
4.5
R1 MCLR C
Brown-out Reset (BOR)
R
PIC18FXXXX
Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
A configuration bit, BOREN, can disable (if clear/ programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for greater than TBOR (parameter #35), the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay TPWRT (parameter #33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling BOR Reset does not automatically enable the PWRT.
4.6
Time-out Sequence
4.2
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F2X20/4X20 devices is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter #33 for details. The PWRT is enabled by clearing configuration bit, PWRTEN.
On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. Table 4-2 shows the Reset conditions for some Special Function Registers, while Table 4-3 shows the Reset conditions for all the registers.
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TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out PWRTEN = 0 66 ms
(1)
Oscillator Configuration HSPLL HS, XT, LP EC, ECIO RC, RCIO INTIO1, INTIO2 Note 1: 2:
PWRTEN = 1
(2)
Exit from Power Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC -- -- --
+ 1024 TOSC + 2 ms
(1)
1024 TOSC + 2 ms(2) 1024 TOSC -- -- --
66 ms
+ 1024 TOSC
(1)
66 ms 66
66 ms(1) ms(1)
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the 4x PLL to lock.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0 IPEN bit 7 Note: Refer to Section 5.14 "RCON Register" for bit definitions. U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-1 POR R/W-1 BOR bit 0
TABLE 4-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h RCON Register 0--1 1100 0--0 uuuu 0--1 11u0--u 1uuu 0--u 10uu 0--u 0uuu RI 1 0 1 u u u TO 1 u 1 1 1 0 PD 1 u 1 u 0 u POR 0 u u u u u BOR 0 u 0 u u u STKFUL 0 u u u u u u 0000h 0--u uuuu u u u u u 1 u 0000h PC + 2 PC + 2 u--u uuuu u--u 00uu u--u u0uu u u u u 0 u u 0 0 u u u u u u u u u STKUNF 0 u u u u u u u 1 1 u u
Condition Power-on Reset RESET Instruction Brown-out MCLR during power managed Run modes MCLR during power managed Idle modes and Sleep mode WDT Time-out during full power or power managed Run mode MCLR during full power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT Time-out during power managed Idle or Sleep modes Interrupt exit from power managed modes
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).
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TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A MCLR Resets WDT Reset RESET Instruction Stack Resets ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A Wake-up via WDT or Interrupt ---0 uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu -u-u(1) uu-u u-uu(1) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 PREINC1 PLUSW1
2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320
POSTDEC0 2220 2320 4220 4320
POSTDEC1 2220 2320 4220 4320
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset ---- xxxx xxxx xxxx ---- 0000 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0000 q000 --00 0101 ---- ---0 0--1 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets ---- uuuu uuuu uuuu ---- 0000 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0000 q000 --00 0101 ---- ---0 0--q qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu qquu --uu uuuu ---- ---u u--u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
FSR1H FSR1L BSR INDF2 POSTINC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON
(4)
2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320
POSTDEC2 2220 2320 4220 4320
TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx --00 0000 --00 0000 0-00 0000 xxxx xxxx xxxx xxxx 0000 0000 --00 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 0000 0000 000- 0000 0000 0111 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 000x 0000 0000 0000 0000 xx-0 x000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets uuuu uuuu uuuu uuuu --00 0000 --00 0000 0-00 0000 uuuu uuuu uuuu uuuu 0000 0000 --00 0000 uuuu uuuu uuuu uuuu --00 0000 0000 0000 0000 0000 000- 0000 0000 0111 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 -010 0000 000x 0000 0000 0000 0000 uu-0 u000 0000 0000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uu-0 u000 0000 0000
ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON PWM1CON ECCPAS CVRCON CMCON TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON1 EECON2
2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset 11-1 1111 00-0 0000 00-0 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 --00 0000 0000 -111 1111 1111 1111 1111 1111 1111 1111 1111(5) ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx(5) ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx0x 0000(5) MCLR Resets WDT Reset RESET Instruction Stack Resets 11-1 1111 00-0 0000 00-0 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 --00 0000 0000 -111 1111 1111 1111 1111 1111 1111 1111 1111(5) ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) ---- xxxx uuuu uuuu uuuu uuuu uuuu uuuu uu0u 0000(5) Wake-up via WDT or Interrupt uu-u uuuu uu-u uuuu(1) uu-u uuuu uuuu uuuu -uuu uuuu uuuu uuuu(1) -uuu uuuu(1) uuuu uuuu -uuu uuuu --uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5)
IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE TRISE TRISD TRISC TRISB TRISA(5) LATE LATD LATC LATB LATA
(5)
2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320 2220 2320 4220 4320
PORTE PORTD PORTC PORTB PORTA(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'.
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FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 0V 1V
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST TPLL
OST Time-out
PLL Time-out Internal Reset Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
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NOTES:
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5.0 MEMORY ORGANIZATION
5.1 Program Memory Organization
There are three memory types in Enhanced MCU devices. These memory types are: * Program Memory * Data RAM * Data EEPROM Data and program memory use separate busses which allow for concurrent access of these types. Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0 "Flash Program Memory" and Section 7.0 "Data EEPROM Memory", respectively. A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all `0's (a NOP instruction). The PIC18F2220 and PIC18F4220 each have 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F2320 and PIC18F4320 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The Program Memory Maps for PIC18F2220/4220 and PIC18F2320/4320 devices are shown in Figure 5-1 and Figure 5-2, respectively.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2220/4220
FIGURE 5-2:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2320/4320
PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
Stack Level 31 Reset Vector 0000h
Stack Level 31 Reset Vector 0000h
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h
0FFFh 1000h
On-Chip Program Memory 1FFFh 2000h
User Memory Space
Read `0'
Read `0'
1FFFFFh 200000h
1FFFFFh 200000h
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User Memory Space
PIC18F2220/2320/4220/4320
5.2 Return Address Stack
5.2.2
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all Resets. There is no RAM associated with stack pointer 00000b. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC (already pointing to the instruction following the CALL). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented. The stack space is not part of either program or data space. The stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack Special File Registers. Data can also be pushed to, or popped from, the stack using the top-of-stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed.
RETURN STACK POINTER (STKPTR)
The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the stack pointer can be 0 through 31. The stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the stack pointer value will be zero. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. (Refer to Section 23.1 "Configuration Bits" for a description of the device configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the stack pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push, and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.
5.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.
FIGURE 5-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 00011 001A34h 00010 000D58h 00001 00000 STKPTR<4:0> 00010
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REGISTER 5-1: STKPTR REGISTER
R/C-0 STKFUL bit 7 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented `0' = Bit is cleared C = Clearable only bit x = Bit is unknown R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0
bit 6(1)
bit 5 bit 4-0
5.2.3
PUSH AND POP INSTRUCTIONS
5.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value.
These Resets are enabled by programming the STVREN bit in Configuration Register 4L. When the STVREN bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. When the STVREN bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR Reset.
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5.3 Fast Register Stack 5.4 PCL, PCLATH and PCLATU
A "fast return" option is available for interrupts. A Fast Register Stack is provided for the Status, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. All interrupt sources will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. Users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the Status, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter.
EXAMPLE 5-1:
CALL SUB1, FAST
FAST REGISTER STACK CODE EXAMPLE
;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK
* * SUB1 * * RETURN FAST
;RESTORE VALUES SAVED ;IN FAST REGISTER STACK
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5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining
An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4.
FIGURE 5-4:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode)
PC+2 PC+4 Internal Phase Clock
PC
Execute INST (PC-2) Fetch INST (PC)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+2) Fetch INST (PC+4)
EXAMPLE 5-2:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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5.7 Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 5.4 "PCL, PCLATH and PCLATU"). The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction `GOTO 000006h' is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 24.0 "Instruction Set Summary" provides further details of the instruction set.
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 000006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
5.7.1
TWO-WORD INSTRUCTIONS
PIC18F2X20/4X20 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to `1's and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the
second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 24.0 "Instruction Set Summary" for further details of the instruction set.
EXAMPLE 5-3:
CASE 1: Object Code
TWO-WORD INSTRUCTIONS
Source Code TSTFSZ MOVFF ADDWF REG1 REG1, REG2 REG3 ; is RAM location 0? ; No, skip this word ; Execute this word as a NOP ; continue code
0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000
Source Code TSTFSZ MOVFF ADDWF REG1 REG1, REG2 REG3 ; is RAM location 0? ; Yes, execute this word ; 2nd word of instruction ; continue code
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5.8 Look-up Tables 5.9 Data Memory Organization
Look-up tables are implemented two ways: * Computed GOTO * Table Reads The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F2X20/4X20 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits of the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user's application. The SFRs start at the last location of Bank 15 (FFFh) and extend towards F80h. Any remaining space beyond the SFRs in the bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as `0's. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the data memory map without banking. See Section 5.12 "Indirect Addressing, INDF and FSR Registers" for indirect addressing details. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 "Access Bank" provides a detailed description of the Access RAM.
5.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-4. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSB = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.
EXAMPLE 5-4:
MOVFW CALL ORG 0xnn00 TABLE ADDWF RETLW RETLW RETLW * * *
COMPUTED GOTO USING AN OFFSET VALUE
OFFSET TABLE PCL 0xnn 0xnn 0xnn
5.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1 "Table Reads and Table Writes".
5.9.1
GENERAL PURPOSE REGISTER FILE
Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F80h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0.
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FIGURE 5-6:
BSR<3:0> = 0000 00h Bank 0 FFh 00h Bank 1 FFh
DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES
Data Memory Map Access RAM GPR GPR 1FFh 200h 000h 07Fh 080h 0FFh 100h
= 0001
Access Bank 7Fh Access RAM High 80h (SFRs) FFh Access RAM Low 00h
= 0010 = 1110
Bank 2 to Bank 14
Unused Read `00h'
When a = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction.
= 1111
00h Bank 15 FFh
Unused SFR
EFFh F00h F7Fh F80h FFFh
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5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as `0's.
TABLE 5-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE4h FE3h FE2h FE1h FE0h
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X20/4X20 DEVICES
Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(2) POSTINC0(2) PREINC0(2) PLUSW0(2) FSR0H FSR0L WREG INDF1(2) POSTINC1(2) PREINC1 FSR1H FSR1L BSR
(2)
Address FDFh FDEh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h
Name INDF2(2) POSTINC2(2) PREINC2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON -- OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2
(2)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON -- -- ECCPAS(1) CVRCON CMCON TMR3H TMR3L T3CON -- SPBRG RCREG TXREG TXSTA RCSTA -- EEADR EEDATA EECON2 EECON1 -- -- -- IPR2 PIR2 PIE2
Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h
Name IPR1 PIR1 PIE1 -- OSCTUNE -- -- -- -- TRISE(1) TRISD(1) TRISC TRISB TRISA -- -- -- -- LATE(1) LATD(1) LATC LATB LATA -- -- -- -- PORTE PORTD(1) PORTC PORTB PORTA
FDDh POSTDEC2(2) PLUSW2(2)
FB7h PWM1CON(1)
FEDh POSTDEC0(2)
FE5h POSTDEC1(2) PLUSW1(2)
Legend: -- = Unimplemented registers, read as `0'. Note 1: This register is not available on PIC18F2X20 devices. 2: This is not a physical register.
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TABLE 5-2:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE INTEDG2 INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx xxxx xxxx n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx Bank Select Register ---- 0000 n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 Details on page: 46, 54 46, 54 46, 54 46, 55 46, 56 46, 56 46, 56 46, 74 46, 74 46, 74 46, 74 46, 85 46, 85 46, 89 46, 90 46, 91 46, 66 46, 66 46, 66 46, 66 46, 66 46, 66 46, 66 46 46, 66 46, 66 46, 66 46, 66 46, 66 47, 66 47, 66 47, 65 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 68 47, 119 47, 119 47, 117
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- bit 21(3)
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- --
Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 0 Low Byte Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 1 High
Indirect Data Memory Address Pointer 1 Low Byte -- -- -- --
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 2 High
Indirect Data Memory Address Pointer 2 Low Byte -- -- -- N
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON T08BIT
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as analog input and read `0' following a Reset. These registers and/or bits are not implemented on the PIC18F2X20 devices and read as `0'. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RE3 reads `0'. This bit is read-only.
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TABLE 5-2:
File Name OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON PWM1CON(5) ECCPAS(5) CVRCON CMCON TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
Bit 7 IDLEN -- -- IPEN Bit 6 IRCF2 -- -- -- Bit 5 IRCF1 IRVST -- -- Bit 4 IRCF0 LVDEN -- RI Bit 3 OSTS LVDL3 -- TO Bit 2 IOFS LVDL2 -- PD Bit 1 SCS1 LVDL1 -- POR Bit 0 SCS0 LVDL0 SWDTEN BOR Value on POR, BOR 0000 q000 --00 0101 --- ---0 0--1 11q0 xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 1111 1111 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 BF SSPM0 SEN 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CHS3 VCFG1 ACQT2 CHS2 VCFG0 ACQT1 CHS1 PCFG3 ACQT0 CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0 --00 0000 --00 0000 0-00 0000 xxxx xxxx xxxx xxxx CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 xxxx xxxx xxxx xxxx CCP2M3 PDC3 PSSAC1 CVR3 CIS CCP2M2 PDC2 PSSAC0 CVR2 CM2 CCP2M1 PDC1 PSSBD1 CVR1 CM1 CCP2M0 PDC0 PSSBD0 CVR0 CM0 --00 0000 0000 0000 0000 0000 000- 0000 0000 0111 xxxx xxxx xxxx xxxx T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 0000 0000 0000 0000 0000 0000 TXEN SREN SYNC CREN -- ADDEN BRGH FERR TRMT OERR TX9D RX9D 0000 -010 0000 000x Details on page: 26, 47 47, 233 47, 246 45, 69, 98 47, 125 47, 125 47, 121 47, 127 47, 127 47, 127 47, 156, 164 47, 164 47, 156, 165 47, 157, 166 47, 167 48, 220 48, 220 48, 211 48, 212 48, 213 48, 134 48, 134 48, 133, 141 48, 134 48, 134 48, 133 48, 149 48, 150 48, 227 48, 221 48, 131 48, 131 48, 129 48, 198 48, 204, 203 48, 202, 203 48, 196 48, 197
Timer1 Register High Byte Timer1 Register Low Byte RD16 T1RUN
Timer2 Register Timer2 Period Register -- TOUTPS3
SSP Receive Buffer/Transmit Register SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. SMP WCOL GCEN CKE SSPOV ACKSTAT D/A SSPEN ACKDT P CKP ACKEN S SSPM3 RCEN R/W SSPM2 PEN UA SSPM1 RSEN
A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM -- -- --
Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte P1M1(5) P1M0(5) DC1B1 DC1B0
Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte -- PRSEN ECCPASE CVREN C2OUT -- PDC6 ECCPAS2 CVROE C1OUT DC2B1 PDC5 ECCPAS1 CVRR C2INV DC2B0 PDC4 ECCPAS0 -- C1INV
Timer3 Register High Byte Timer3 Register Low Byte RD16 T3CCP2
USART Baud Rate Generator USART Receive Register USART Transmit Register CSRC SPEN TX9 RX9
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as analog input and read `0' following a Reset. These registers and/or bits are not implemented on the PIC18F2X20 devices and read as `0'. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RE3 reads `0'. This bit is read-only.
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TABLE 5-2:
File Name EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE TRISE(5) TRISD(5) TRISC TRISB TRISA LATE(5) LATD(5) LATC LATB LATA PORTE PORTD PORTC PORTB PORTA Legend: Note 1: 2: 3: 4: 5: 6:
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 0000 0000 0000 0000 WRERR BCLIP BCLIF BCLIE SSPIP SSPIF SSPIE TUN3 -- WREN LVDIP LVDIF LVDIE CCP1IP CCP1IF CCP1IE TUN2 WR TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE TUN1 RD CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE TUN0 xx-0 x000 11-1 1111 00-0 0000 00-0 0000 1111 1111 0000 0000 0000 0000 --00 0000 0000 -111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Read PORTE pins, Write PORTE Data Latch(5) ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx0x 0000 RE3(6) Details on page: 48, 81 48, 84 48, 72, 81 48, 73, 82 49, 97 49, 93 49, 95 49, 96 49, 92 49, 94 23, 49 49, 112 49, 110 49, 108 49, 106 49, 103 49, 113 49, 110 49, 108 49, 106 49, 103 49, 113 49, 110 49, 108 49, 106 49, 103
EEPROM Address Register EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD OSCFIP OSCFIF OSCFIE PSPIP(5) PSPIF(5) PSPIE(5) -- IBF CFGS CMIP CMIF CMIE ADIP ADIF ADIE -- OBF -- -- -- -- RCIP RCIF RCIE TUN5 IBOV FREE EEIP EEIF EEIE TXIP TXIF TXIE TUN4 PSPMODE
Data Direction bits for PORTE(5)
Data Direction Control Register for PORTD Data Direction Control Register for PORTC Data Direction Control Register for PORTB TRISA7(2) -- TRISA6(1) -- Data Direction Control Register for PORTA -- -- -- Read/Write PORTE Data Latch
Read/Write PORTD Data Latch Read/Write PORTC Data Latch Read/Write PORTB Data Latch LATA<7>(2) LATA<6>(1) Read/Write PORTA Data Latch -- -- -- --
Read PORTD pins, Write PORTD Data Latch Read PORTC pins, Write PORTC Data Latch Read PORTB pins, Write PORTB Data Latch(4) RA7(2) RA6(1) Read PORTA pins, Write PORTA Data Latch
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as analog input and read `0' following a Reset. These registers and/or bits are not implemented on the PIC18F2X20 devices and read as `0'. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to `0'. Otherwise, RE3 reads `0'. This bit is read-only.
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5.10 Access Bank 5.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read `0's and writes will have no effect (see Figure 5-7). A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all `0's and all writes are ignored. The Status register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR since the 12-bit addresses are embedded into the instruction word. Section 5.12 "Indirect Addressing, INDF and FSR Registers" provides a description of indirect addressing which allows linear addressing of the entire RAM space.
The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the `a' bit (for access bit). When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits.
FIGURE 5-7:
DIRECT ADDRESSING
Direct Addressing
BSR<7:4> 0 0 0 0
BSR<3:0>
7
From Opcode(3)
0
Bank Select(2)
Location Select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h
Data Memory(1)
0FFh Bank 0
1FFh Bank 1
EFFh Bank 14
FFFh Bank 15
Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
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5.12 Indirect Addressing, INDF and FSR Registers
If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all `0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the status bits are not affected.
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation. The FSR register contains a 12-bit address which is shown in Figure 5-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer); this is indirect addressing. Example 5-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions.
5.12.1
INDIRECT ADDRESSING OPERATION
Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSR will be modified during indirect addressing. When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the Status register. For example, if the indirect address causes the FSR to equal `0', the Z bit will not be set. Auto-incrementing or auto-decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its use for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. The WREG offset range is -128 to +127. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set) while an indirect write will be equivalent to a NOP (status bits are not affected). If an indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register but no pre- or post-increment/decrement is performed.
EXAMPLE 5-5:
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING
NEXT
FSR0,0x100 ; POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? GOTO NEXT ; NO, clear next CONTINUE ; YES, continue
LFSR CLRF
There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12 bits wide. To store the 12 bits of addressing information, two 8-bit registers are required: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used.
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FIGURE 5-8: INDIRECT ADDRESSING OPERATION
RAM 0h
Instruction Executed Opcode Address FFFh 12 File Address = access of an indirect addressing register
BSR<3:0> Instruction Fetched Opcode 4
12 8 File
12
FSR
FIGURE 5-9:
INDIRECT ADDRESSING
Indirect Addressing
FSRnH:FSRnL 3 11 Location Select 0 7 0 0
0000h
Data Memory(1)
0FFFh Note 1: For register file map detail, see Table 5-1.
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5.13 Status Register
The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. The Status register can be the operand for any instruction as with any other register. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Status register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the Z, C, DC, OV or N bits in the Status register. For other instructions not affecting any status bits, see Table 24-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0
bit 7-5 bit 4
Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register.
bit 3
bit 2
bit 1
bit 0
C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions. 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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5.14 RCON Register
The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is `1' on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected.
REGISTER 5-3:
RCON REGISTER
R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned (TBLPTRL<0> = 0). The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.
6.1
Table Reads and Table Writes
In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
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FIGURE 6-2: TABLE WRITE OPERATION
Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory".
6.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled - the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.3 "Reading the Flash Program Memory" regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software.
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled.
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REGISTER 6-1: EECON1 REGISTER
R/W-x EEPGD bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program Flash or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation - TBLPTR<5:0> are ignored) 0 = Perform write only WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (any Reset during self-timed programming) 0 = The write operation completed normally Note: bit 2 When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: Write Enable bit 1 = Allows erase or write cycles 0 = Inhibits erase or write cycles WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as `0' W = Writable bit `0' = Bit is cleared x = Bit is unknown - n = Value at POR `1' = Bit is set
bit 1
bit 0
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6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the TBLPTR (TBLPTR<21:3>) will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.
6.2.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the device ID, the user ID and the configuration bits. The table pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21 bits.
TABLE 6-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
ERASE - TBLPTR<21:6> LONG WRITE - TBLPTR<21:3> READ or WRITE - TBLPTR<21:0>
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6.3 Reading the Flash Program Memory
The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.
The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
Odd (High) Byte
Even (Low) Byte
TBLPTR LSB = 1 Instruction Register (IR) TABLAT Read Register
TBLPTR LSB = 0
EXAMPLE 6-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVFW MOVWF TBLRD*+ MOVFW MOVWF
TABLAT WORD_EVEN TABLAT WORD_ODD
; read into TABLAT and increment TBLPTR ; get data ; read into TABLAT and increment TBLPTR ; get data
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6.4 Erasing Flash Program Memory
6.4.1
The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased; TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access program Flash and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2) and starts the actual erase operation. It is not necessary to load the TABLAT register with any data as it is ignored. For protection, the write initiate sequence using EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. Load Table Pointer with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts.
3. 4. 5. 6. 7. 8. 9.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1,EEPGD EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON2,WR INTCON,GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF ; ; ; ; point to Flash program memory enable write to memory enable Row Erase operation disable interrupts
; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts
Required Sequence
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6.5 Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxxx7
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 6.4.1 "Flash Program Memory Erase Sequence"). Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable byte writes.
8. 9. 10. 11. 12. 13. 14. 15. 16.
Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Repeat steps 6-14 seven times, to write 64 bytes. Verify the memory (table read).
This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3.
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVFW MOVWF DECFSZ GOTO MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF WRITE_BUFFER_BACK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PROGRAM_LOOP MOVLW MOVWF WRITE_WORD_TO_HREGS MOVFW MOVWF TBLWT+* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1,CFGS EECON1,EEPGD EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE 8 COUNTER_HI BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L 8 COUNTER POSTINC0 TABLAT ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data and increment FSR0 done? repeat D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer
; Load TBLPTR with the base ; address of the memory block
; 6 LSB = 0
; update buffer word and increment FSR0 ; update buffer word
; 6 LSB = 0 ; ; ; ; ; ; ; point to PROG/EEPROM memory point to Flash program memory enable write to memory enable Row Erase operation disable interrupts Required sequence write 55H
; write AAH ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer
; number of bytes in holding register
; ; ; ;
DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS
get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full
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EXAMPLE 6-3:
PROGRAM_MEMORY BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ GOTO BCF INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE COUNTER_HI PROGRAM_LOOP EECON1,WREN ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ; disable write to memory
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2
WRITE VERIFY
6.6
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
Flash Program Operation During Code Protection
See Section 23.0 "Special Features of the CPU" (Section 23.5 "Program Verification and Code Protection") for details on code protection of Flash program memory.
6.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, users can check the WRERR bit and rewrite the location.
TABLE 6-2:
Name TBLPTRU TBPLTRH TBLPTRL TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Legend:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7 -- Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer High Byte (TBLPTR<7:0>) Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE EEPGD OSCFIP OSCFIF OSCFIE CFGS CMIP CMIF CMIE -- -- -- -- INTE FREE EEIP EEIF EEIE RBIE WRERR BCLIP BCLIF BCLIE TMR0IF WREN LVDIP LVDIF LVDIE INTF WR TMR3IP TMR3IF TMR3IE RBIF RD CCP2IP CCP2IF CCP2IE EEPROM Control Register 2 (not a physical register)
0000 000x 0000 000u -- --
xx-0 x000 uu-0 u000 11-1 1111 ---1 1111 00-0 0000 ---0 0000 00-0 0000 ---0 0000
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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7.0 DATA EEPROM MEMORY
The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled; the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 "Table Reads and Table Writes" regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.
The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Table 26-1 in Section 26.0 "Electrical Characteristics") for exact limits.
7.1
EEADR
The address register can address 256 bytes of data EEPROM.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed.
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REGISTER 7-1: EECON1 REGISTER
R/W-x EEPGD bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally Note: bit 2 When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is completed RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit - n = Value at POR S = Settable only `1' = Bit is set U = Unimplemented bit, read as `0' W = Writable bit `0' = Bit is cleared x = Bit is unknown
bit 1
bit 0
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7.3 Reading the Data EEPROM Memory
After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation).
7.4
Writing to the Data EEPROM Memory
7.5
Write Verify
To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM. The WREN bit is not cleared by hardware.
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.
EXAMPLE 7-1:
MOVLW MOVWF BCF BSF MOVF
DATA EEPROM READ
DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA
EXAMPLE 7-2:
MOVLW MOVWF MOVLW MOVWF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF SLEEP BCF
DATA EEPROM WRITE
DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, WREN INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write AAh Set WR bit to begin write Enable Interrupts
Required Sequence
EECON1, WREN
; Wait for interrupt to signal write complete ; Disable writes
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7.7 Operation During Code-Protect 7.8 Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in configuration words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal Data EEPROM regardless of the state of the code-protect configuration bit. Refer to Section 23.0 "Special Features of the CPU" for additional information. The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124 or D124A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A.
EXAMPLE 7-3:
CLRF BCF BCF BCF BSF LOOP BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA BCF BSF
DATA EEPROM REFRESH ROUTINE
EEADR EECON1, EECON1, INTCON, EECON1, CFGS EEPGD GIE WREN ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete
EECON1, RD 55h EECON2 AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F Loop EECON1, WREN INTCON, GIE
; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts
TABLE 7-1:
Name INTCON EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 Legend: Bit 7
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 6 PEIE/GIEL Bit 5 TMR0IE Bit 4 INTE Bit 3 RBIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR Value on all other Resets
GIE/GIEH
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 -- --
EEPROM Address Register EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD OSCFIP OSCFIF OSCFIE CFGS CMIP CMIF CMIE -- -- -- -- FREE EEIP EEIF EEIE WRERR BCLIP BCLIF BCLIE WREN LVDIP LVDIF LVDIE WR TMR3IP TMR3IF TMR3IE RD CCP2IF
xx-0 x000 uu-0 u000
CCP2IP 11-1 1111 ---1 1111 00-0 0000 ---0 0000 CCP2IE 00-0 0000 ---0 0000
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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8.0
8.1
8 X 8 HARDWARE MULTIPLIER
Introduction
Making the 8 x 8 multiplier execute in a single-cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 8-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply.
An 8 x 8 hardware multiplier is included in the ALU of the PIC18F2X20/4X20 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4.0 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
8.2
Operation
EXAMPLE 8-1:
MOVF MULWF
Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
ARG1, W ARG2
EXAMPLE 8-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
; Test Sign Bit ; PRODH = PRODH ; - ARG2
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Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 8-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L)
RES3:RES0
= =
RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216)
EXAMPLE 8-4:
MOVF MULWF MOVFF MOVFF
16 x 16 SIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ;
EXAMPLE 8-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ;
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F
MOVF MULWF MOVFF MOVFF
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs' Most Significant bit (MSb) is tested and the appropriate subtractions are done.
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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9.0 INTERRUPTS
The PIC18F2320/4320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority (most interrupt sources have priority bits) The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.
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FIGURE 9-1: INTERRUPT LOGIC
Wake-up if in Power Managed Mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0008h
PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation
GIEH/GIE IPE IPEN GIEL/PEIE IPEN
PSPIF PSPIE PSPIP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Additional Peripheral Interrupts INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0018h
ADIF ADIE ADIP RCIF RCIE RCIP
GIEL\PEIE
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9.1 INTCON Registers
Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 9-1:
INTCON REGISTER
R/W-0 GIE/GIEH bit 7 R/W-0 PEIE/GIEL R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 9-2: INTCON2 REGISTER
R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as `0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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REGISTER 9-3: INTCON3 REGISTER
R/W-1 INT2IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as `0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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9.2 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag registers (PIR1, PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
bit 6
ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 OSCFIF bit 7 bit 7 R/W-0 CMIF U-0 -- R/W-0 EEIF R/W-0 BCLIF R/W-0 LVDIF R/W-0 TMR3IF R/W-0 CCP2IF bit 0
OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as `0' EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow CCP2IF: CCPx Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
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9.3 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 PSPIE bit 7
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit 0
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
bit 6
ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 OSCFIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CMIE U-0 -- R/W-0 EEIE R/W-0 BCLIE R/W-0 LVDIE R/W-0 TMR3IE R/W-0 CCP2IE bit 0
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
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9.4 IPR Registers
The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 PSPIP bit 7
(1)
R/W-1 ADIP
R/W-1 RCIP
R/W-1 TXIP
R/W-1 SSPIP
R/W-1 CCP1IP
R/W-1 TMR2IP
R/W-1 TMR1IP bit 0
bit 7
PSPIP(1): Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit set.
bit 6
ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 OSCFIP bit 7 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 CMIP U-0 -- R/W-1 EEIP R/W-1 BCLIP R/W-1 LVDIP R/W-1 TMR3IP R/W-1 CCP2IP bit 0
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
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9.5 RCON Register
The RCON register contains bits used to determine the cause of the last Reset or wake-up from power managed mode. RCON also contains the bit that enables interrupt priorities (IPEN).
REGISTER 9-10:
RCON REGISTER
R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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9.6 INTn Pin Interrupts 9.8 PORTB Interrupt-on-Change
External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from the power managed modes if bit INTxE was set prior to going into power managed modes. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section 5.3 "Fast Register Stack"), the user may need to save the WREG, Status and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine.
9.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h) in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module.
EXAMPLE 9-1:
MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere
W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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NOTES:
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10.0 I/O PORTS
10.1
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Data Latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 10-1.
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 23.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins, RA3:RA0 and RA5, as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA4 is configured as a digital input.
FIGURE 10-1:
GENERIC I/O PORT OPERATION
RD LAT Data Bus WR LAT or Port
D
Q I/O pin(1)
CK Data Latch D Q
WR TRIS
CK TRIS Latch Input Buffer
RD TRIS
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input and an open-drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the RA pins even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
Q
D EN EN
RD Port Note 1: I/O pins have diode protection to VDD and VSS.
EXAMPLE 10-1:
CLRF PORTA ; ; ; LATA ; ; ; 0x07 ; ADCON1 ; 0xCF ; ; ; TRISA ; ;
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs
CLRF
MOVLW MOVWF MOVLW
MOVWF
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FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN
RD LATA Data Bus WR LATA or PORTA
RD LATA Data Bus WR LATA or PORTA
D
Q VDD Q
D
Q Q I/O pin(1)
CK
P
CK
Data Latch D WR TRISA Analog Input Mode Q Q N I/O pin
(1)
N
Data Latch D WR TRISA Q Q VSS Schmitt Trigger Input Buffer
CK
VSS
CK
TRIS Latch
TRIS Latch
RD TRISA RD TRISA Q D EN RD PORTA SS Input (RA5 only) TMR0 Clock Input To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: I/O pins have protection diodes to VDD and VSS. RD PORTA TTL Input Buffer
Q
D EN EN
FIGURE 10-3:
RA6 Enable Data Bus RD LATA
BLOCK DIAGRAM OF RA6 PIN
FIGURE 10-5:
RA7 Enable Data Bus RD LATA
BLOCK DIAGRAM OF RA7 PIN
To Oscillator
WR LATA or PORTA
D
Q
VDD P
CK
Q
WR LATA or PORTA
D
Q
VDD P
CK
Q
Data Latch D WR TRISA Q N I/O pin(1) WR TRISA
Data Latch D Q N I/O pin(1)
CK
Q
VSS
CK
Q
VSS
TRIS Latch RD TRISA ECIO or RCIO Enable RD TRISA RA7 Enable
TRIS Latch
TTL Input Buffer
TTL Input Buffer
Q
D EN
Q
D EN
RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS.
RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS.
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TABLE 10-1:
RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC2/CLKO/RA6 OSC1/CLKI/RA7
PORTA FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer TTL TTL TTL TTL ST TTL TTL TTL Function Input/output or analog input. Input/output or analog input. Input/output, analog input, VREF- or Comparator VREF output. Input/output, analog input or VREF+. Input/output, external clock input for Timer0 or Comparator 1 output. Output is open-drain type. Input/output, analog input, Slave Select input for Synchronous Serial Port, Low-Voltage Detect input or Comparator 2 output. OSC2, clock output or I/O pin. OSC1, clock input or I/O pin.
Name
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2:
Name PORTA LATA TRISA ADCON1 CMCON CVRCON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 RA7(1) Bit 6 RA6(1) Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR xx0x 0000 xxxx xxxx 1111 1111 PCFG2 CM2 CVR2 PCFG1 CM1 CVR1 PCFG0 CM0 CVR0 --00 0000 0000 0111 000- 0000 Value on all other Resets uu0u 0000 uuuu uuuu 1111 1111 --00 0000 0000 0111 000- 0000
LATA7(1) -- C2OUT CVREN
LATA6(1) LATA Data Latch Register -- C1OUT CVROE VCFG1 C2INV CVRR VCFG0 C1INV -- PCFG3 CIS CVR3
TRISA7(1) TRISA6(1) PORTA Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'.
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10.2 PORTB, TRISB and LATB Registers
This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit RBIF.
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB.
b)
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0).
EXAMPLE 10-2:
CLRF ; ; ; LATB ; ; ; 0x0F ; ADCON1 ; ; ; 0xCF ; ; ; TRISB ; ; ; PORTB
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB<4:0> as digital I/O pins (required if config bit PBADEN is set) Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
CLRF
FIGURE 10-6:
MOVLW MOVWF
BLOCK DIAGRAM OF RB7:RB5 PINS
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(1)
RBPU(2)
MOVLW
Data Bus WR LATB or PORTB
MOVWF
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as `0'; RB7:RB5 are configured as digital inputs. By programming the configuration bit, PBADEN (CONFIG3H<1>), RB4:RB0 will alternatively be configured as digital inputs on POR. Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>).
WR TRISB
CK
ST Buffer
RD TRISB
RD LATB Latch Q RD PORTB EN Set RBIF Q1 D
Q From other RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: 2:
D RD PORTB EN Q3
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
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FIGURE 10-7:
RBPU(2) Analog Input Mode Data Bus WR LATB or PORTB D Q I/O pin CK Data Latch D WR TRISB Q WR TRISB TTL Input Buffer
(1)
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD Weak P Pull-up
FIGURE 10-8:
BLOCK DIAGRAM OF RB4 PIN
VDD Weak P Pull-up I/O pin(1) CK TRIS Latch D Q CK TTL Input Buffer
RBPU(2) Data Bus WR LATB or PORTB Data Latch D Q
CK TRIS Latch
RD TRISB
RD TRISB RD LATB Q D EN EN RD PORTB INTx Schmitt Trigger Buffer
RD LATB Latch Q RD PORTB EN Set RBIF Q1 D
Q From RB7:RB5 To A/D Converter Note 1: 2:
D RD PORTB EN Q3
To A/D Converter Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
FIGURE 10-9:
BLOCK DIAGRAM OF RB3/CCP2 PIN
VDD RBPU Analog Input Mode 0 D Q VDD P 1 Weak P Pull-up
Port/CCP2 Select CCP2 Data Out
RD LATC Data Bus WR LATB or PORTB
CK Data Latch D Q N VSS TTL Input Buffer RB3 pin(1)
WR TRISB
CK TRIS Latch
RD TRISC Q D EN EN RD PORTB CCP2 Input Analog Input Mode To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. Schmitt Trigger
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TABLE 10-3:
Name RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2
PORTB FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 Buffer TTL /ST
(1) (2)
Function Input/output pin, analog input or external interrupt input 0. Internal software programmable weak pull-up. Input/output pin, analog input or external interrupt input 1. Internal software programmable weak pull-up. Input/output pin, analog input or external interrupt input 2. Internal software programmable weak pull-up. Input/output pin or analog input. Capture2 input/Compare2 output/ PWM output when CCP2MX configuration bit is set(4). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change) or analog input. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage ICSP enable pin. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.
TTL(1)/ST(2) TTL(1)/ST(2) TTL(1)/ST(3)
RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: 2: 3: 4: 5:
bit 4 bit 5 bit 6 bit 7
TTL TTL/ST(5) TTL/ST(5) TTL/ST(5)
TTL = TTL input, ST = Schmitt Trigger input This buffer is a TTL input when configured as digital I/O. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when configured as the CCP2 input. A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on. This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 10-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ADCON1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxq qqqq xxxx xxxx 1111 1111 INT0IE INT2IE VCFG0 RBIE -- INT1IE PCFG3 TMR0IF TMR0IP -- PCFG2 INT0IF -- INT2IF PCFG1 RBIF RBIP INT1IF PCFG0 0000 000x 1111 -1-1 11-0 0-00 --00 0000 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 000u 1111 -1-1 11-0 0-00 --00 0000
LATB Data Latch Register PORTB Data Direction Register GIE/GIEH PEIE/GIEL TMR0IE RBPU INT2IP -- INT1IP -- -- VCFG1 INTEDG0 INTEDG1 INTEDG2
x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB.
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10.3 PORTC, TRISC and LATC Registers
Note: On a Power-on Reset, these pins are configured as digital inputs.
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-5). The pins have Schmitt Trigger input buffers. RC1 is normally configured by configuration bit, CCP2MX (CONFIG3H<0>), as the default peripheral pin of the CCP2 module (default/erased state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents even though a peripheral device may be overriding one or more of the pins.
EXAMPLE 10-3:
CLRF PORTC
INITIALIZING PORTC
; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs
CLRF
LATC
MOVLW
0xCF
MOVWF
TRISC
FIGURE 10-10:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2) Peripheral Data Out VDD
RD LATC Data Bus WR LATC or WR PORTC 0 D Q P CK Q 1 I/O pin(1)
Data Latch D WR TRISC Q Q N
CK
TRIS Latch VSS Schmitt Trigger
RD TRISC Peripheral Output Enable(3)
Q
D EN
RD PORTC Peripheral Data In Note 1: 2: 3: I/O pins have diode protection to VDD and VSS. Port/Peripheral Select signal selects between port data (output) and peripheral output. Peripheral Output Enable is only active if Peripheral Select is active.
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TABLE 10-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2
PORTC FUNCTIONS
Bit# bit 0 bit 1 Buffer Type ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin, Timer1 oscillator input or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is disabled. Input/output port pin, Capture1 input/Compare1 output/PWM1 output or enhanced PWM output A(1). RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin, Addressable USART Asynchronous Transmit or Addressable USART Synchronous Clock. Input/output port pin, Addressable USART Asynchronous Receive or Addressable USART Synchronous Data.
RC2/CCP1/P1A(1) RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
ST ST ST ST ST ST
Legend: ST = Schmitt Trigger input Note 1: Enhanced PWM output is available only on PIC18F4X20 devices.
TABLE 10-6:
Name PORTC LATC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111
Bit 7 RC7
LATC Data Latch Register PORTC Data Direction Register
Legend: x = unknown, u = unchanged
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10.4
Note:
PORTD, TRISD and LATD Registers
PORTD is only available on PIC18F4X20 devices.
PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Three of the PORTD pins are multiplexed with outputs P1B, P1C and P1D of the Enhanced CCP module. The operation of these additional PWM output pins is covered in greater detail in Section 16.0 "Enhanced Capture/Compare/PWM (ECCP) Module". Note: On a Power-on Reset, these pins are configured as digital inputs.
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 "Parallel Slave Port" for additional information on the Parallel Slave Port (PSP). Note: When the enhanced PWM mode is used with either dual or quad outputs, the PSP functions of PORTD are automatically disabled.
EXAMPLE 10-4:
CLRF PORTD ; ; ; ; ; ; ; ; ; : ; ;
INITIALIZING PORTD
Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs
CLRF
LATD
MOVLW
0xCF
MOVWF
TRISD
FIGURE 10-11:
BLOCK DIAGRAM OF RD7:RD5 PINS
PORTD/CCP1 Select CCP Data Out PSPMODE
RD LATD Data Bus WR LATD or PORTD D Q 0 VDD P 1
CK
Q
Data Latch D WR TRISD Q Q I/O pin(1) 0 N VSS TTL Buffer RD TRISD Q RD PORTD D 0 0 EN EN Schmitt Trigger Input Buffer 1
CK
TRIS Latch PSP Read 1
PSP Write Note 1:
1 I/O pins have diode protection to VDD and VSS.
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FIGURE 10-12: BLOCK DIAGRAM OF RD4:RD0 PINS
PORTD/CCP1 Select PSPMODE
RD LATD Data Bus WR LATD or PORTD D Q VDD
CK
Q
P
Data Latch D WR TRISD Q I/O pin(1) CK Q 0 N VSS TTL Buffer RD TRISD Q RD PORTD D 0 0 EN EN Schmitt Trigger Input Buffer 1 TRIS Latch PSP Read 1
PSP Write Note 1:
1
I/O pins have diode protection to VDD and VSS.
TABLE 10-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D
PORTD FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL
(1)
Function Input/output port pin or Parallel Slave Port bit 0. Input/output port pin or Parallel Slave Port bit 1. Input/output port pin or Parallel Slave Port bit 2. Input/output port pin or Parallel Slave Port bit 3. Input/output port pin or Parallel Slave Port bit 4. Input/output port pin, Parallel Slave Port bit 5 or enhanced PWM output P1B. Input/output port pin, Parallel Slave Port bit 6 or enhanced PWM output P1C. Input/output port pin, Parallel Slave Port bit 7 or enhanced PWM output P1D.
ST/TTL(1) ST/TTL(1) ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-8:
Name PORTD LATD TRISD TRISE CCP1CON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 PSPMODE DC1B0 -- PORTE Data Direction bits 0000 -111 0000 0000 CCP1M3 CCP1M2 CCP1M1 CCP1M0 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 -111 0000 0000
Bit 7 RD7
LATD Data Latch Register PORTD Data Direction Register IBF P1M1 OBF P1M0 IBOV DC1B1
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PORTD.
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10.5 PORTE, TRISE and LATE Registers
10.5.1 PORTE IN 28-PIN DEVICES
For PIC18F2X20 devices, PORTE is only available when Master Clear functionality is disabled (CONFIG3H<7> = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described.
Depending on the particular PIC18F2X20/4X20 device selected, PORTE is implemented in two different ways. For PIC18F4X20 devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/ AN7/CS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs.
FIGURE 10-13:
BLOCK DIAGRAM OF RE2:RE0 PINS
RD LATE Data Bus WR LATE or PORTE
D
Q I/O pin(1)
CK Data Latch D Q Schmitt Trigger Input Buffer
WR TRISE
CK TRIS Latch
RD TRISE
The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation is explained in Register 10-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled.
Q
D EN EN
RD PORTE To Analog Converter Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-14:
MCLRE Data Bus RD TRISE
BLOCK DIAGRAM OF MCLR/VPP/RE3 PIN
MCLR/VPP/ RE3 Schmitt Trigger
EXAMPLE 10-5:
CLRF PORTE ; ; ; LATE ; ; ; 0x0A ; ADCON1 ; 0x03 ; ; ; TRISC ; ; ;
INITIALIZING PORTE
Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as inputs RE<1> as outputs RE<2> as inputs
RD LATE Latch Q D EN
CLRF
RD PORTE High-Voltage Detect Internal MCLR Filter Low-Level MCLR Detect HV
MOVLW MOVWF MOVLW
MOVWF
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REGISTER 10-1: TRISE REGISTER
R-0 IBF bit 7 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as `0' TRISE2: RE2 Direction Control bit 1 = Input 0 = Output TRISE1: RE1 Direction Control bit 1 = Input 0 = Output TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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TABLE 10-9:
Name RE0/AN5/RD
PORTE FUNCTIONS
Bit# bit 0 Buffer Type ST/TTL(1) Function Input/output port pin, analog input or read control input in Parallel Slave Port mode. For RD (PSP Control mode): 1 = PSP is Idle 0 = Read operation. Reads PORTD register (if chip selected). Input/output port pin, analog input or write control input in Parallel Slave Port mode. For WR (PSP Control mode): 1 = PSP is Idle 0 = Write operation. Writes PORTD register (if chip selected). Input/output port pin, analog input or chip select control input in Parallel Slave Port mode. For CS (PSP Control mode): 1 = PSP is Idle 0 = External device is selected Input only port pin or programming voltage input (if MCLR is disabled); Master Clear input or programming voltage input (if MCLR is enabled).
RE1/AN6/WR
bit 1
ST/TTL(1)
RE2/AN7/CS
bit 2
ST/TTL(1)
MCLR/VPP/RE3
bit 3
ST
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name PORTE LATE TRISE ADCON1 Legend: Note 1: Bit 7 -- -- IBF -- Bit 6 -- -- OBF -- Bit 5 -- -- IBOV VCFG1 Bit 4 -- -- PSPMODE VCFG0 Bit 3 RE3(1) -- -- PCFG3 Bit 2 RE2 Bit 1 RE1 Bit 0 RE0 Value on POR, BOR ---- q000 ---- -xxx 0000 -111 --00 0000 Value on all other Resets ---- q000 ---- -uuu 0000 -111 --00 0000
LATE Data Latch Register PORTE Data Direction bits PCFG2 PCFG1 PCFG0
x = unknown, u = unchanged, - = unimplemented, read as `0', q = value depends on condition. Shaded cells are not used by PORTE. Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
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10.6
Note:
Parallel Slave Port
The Parallel Slave Port is only available on PIC18F4X20 devices.
The timing for the control signals in Write and Read modes is shown in Figure 10-16 and Figure 10-17, respectively.
In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation, as long as the Enhanced CCP module is not operating in dual output or quad output PWM mode. In Slave mode, the port is asynchronously readable and writable by the external world. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits PFCG3:PFCG0 (ADCON1<3:0>) must also be set to `1010'. A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken.
FIGURE 10-15:
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
One bit of PORTD
Data Bus D WR LATD or WR PORTD CK Data Latch Q RD PORTD D EN EN TTL Q RDx pin
RD LATD
Set Interrupt Flag PSPIF (PIR1<7>)
PORTE Pins Read TTL RD
Chip Select TTL Write TTL
CS
WR
Note:
I/O pins have diode protection to VDD and VSS.
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FIGURE 10-16: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
FIGURE 10-17:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name PORTD LATD TRISD PORTE LATE TRISE INTCON PIR1 PIE1 IPR1 ADCON1 Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 -- -- PSPMODE INT0IE TXIF TXIE TXIP VCFG0 RE3 -- -- RBIE SSPIF SSPIE SSPIP PCFG3 RE2 RE1 RE0 ---- 0000 ---- -xxx 0000 -111 0000 000x 0000 0000 0000 0000 1111 1111 --00 0000 RBIF TMR1IF TMR1IE TMR1IP PCFG0 LATE Data Latch bits PORTE Data Direction bits TMR0IF CCP1IF CCP1IE CCP1IP PCFG2 INT0IF TMR2IF TMR2IE TMR2IP PCFG1 -- -- IBOV TMR0IF RCIF RCIE RCIP VCFG1 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 ---- 0000 ---- -uuu 0000 -111 0000 000u 0000 0000 0000 0000 1111 1111 --00 0000
Port Data Latch when written; Port pins when read LATD Data Latch bits PORTD Data Direction bits -- -- IBF GIE/ GIEH PSPIF PSPIE PSPIP -- -- -- OBF PEIE/ GIEL ADIF ADIE ADIP --
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port.
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NOTES:
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11.0 TIMER0 MODULE
The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection.
REGISTER 11-1:
T0CON: TIMER0 CONTROL REGISTER
R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus RA4/T0CKI/C1OUT pin FOSC/4 0 8 0 1 Programmable Prescaler T0SE 1 Sync with Internal Clocks (2 TCY delay) TMR0
3
T0PS2, T0PS1, T0PS0 T0CS
PSA
Set Interrupt Flag bit TMR0IF on Overflow
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
RA4/T0CKI/C1OUT FOSC/4 pin
0 0 1 Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS PSA 8 8 TMR0H 8 Data Bus<7:0> 1 Sync with Internal Clocks (2 TCY delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow
T0SE
Read TMR0L Write TMR0L
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
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11.1 Timer0 Operation
11.2.1
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution).
11.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep mode, since the timer requires clock cycles, even when T0CS is set.
11.4
16-Bit Mode Timer Reads and Writes
11.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x....etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment.
TMR0H is not the high byte of the timer/counter in 16-bit mode but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0, without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
TABLE 11-1:
Name TMR0L TMR0H INTCON T0CON TRISA Legend: Note 1:
REGISTERS ASSOCIATED WITH TIMER0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 0000 0000 INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 0000 000x 1111 1111 1111 1111 Value on all other Resets uuuu uuuu 0000 0000 0000 000u 1111 1111 1111 1111
Bit 7
Timer0 Module Low Byte Register Timer0 Module High Byte Register GIE/GIEH TMR0ON RA7(1) PEIE/GIEL T08BIT RA6(1) TMR0IE T0CS
PORTA Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H.
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NOTES:
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12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from CCP module special event trigger * Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in power managed modes. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead.
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0 RD16 bit 7 R-0 T1RUN R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1 (External Clock): 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0 (Internal Clock): This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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12.1 Timer1 Operation
Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input, or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. The TRISC1:TRISC0 values are ignored and the pins read as `0'. Timer1 also has an internal "Reset input". This Reset can be generated by the CCP module (see Section 15.4.4 "Special Event Trigger").
FIGURE 12-1:
TMR1IF Overflow Interrupt Flag bit
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger TMR1 TMR1H CLR TMR1L TMR1ON On/Off 0 1 T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS Peripheral Clocks Synchronize det Synchronized Clock Input
T1CKI/T1OSO T1OSI
T1OSC T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock
1
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
TMR1H
Data Bus<7:0>
8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 High Byte TMR1
8 CCP Special Event Trigger Synchronized Clock Input
0 CLR TMR1L 1 TMR1ON on/off 1 T1SYNC Prescaler 1, 2, 4, 8 0 2 TMR1CS
T1OSC T1CKI/T1OSO T1OSCEN Enable Oscillator(1)
Synchronize det
T1OSI
FOSC/4 Internal Clock
Peripheral Clocks T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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12.2 Timer1 Oscillator 12.3
A crystal oscillator circuit is built-in between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.
Timer1 Oscillator Layout Considerations
The Timer1 oscillator circuit draws very little power during operation. Due to the low power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane.
FIGURE 12-3:
EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR
PIC18FXXXX
T1OSI XTAL 32.768 kHz T1OSO
C1 33 pF
FIGURE 12-4:
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
VDD
C2 33 pF Note: See the Notes with Table 12-1 for additional information about capacitor selection.
VSS OSC1 OSC2
TABLE 12-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4)
Freq 32 kHz 27 C1 pF(1) C2 27 pF(1)
Note: Not drawn to scale.
RC0 RC1
RC2
Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
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12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
12.5
Resetting Timer1 Using a CCP Trigger Output
12.7
If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion if the A/D module is enabled (see Section 15.4.4 "Special Event Trigger" for more information). Note: The special event triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>).
Using Timer1 as a Real-Time Clock
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1.
Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 "Timer1 Oscillator" above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
12.6
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads.
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EXAMPLE 12-1:
RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN RTCisr BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H,7 PIR1,TMR1IF secs,F .59 secs secs mins,F .59 mins mins hours,F .23 hours .01 hours ; ; ; ; ; ; ; ; ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed? 0x80 TMR1H TMR1L b'00001111' T1OSC secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ;
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
; Enable Timer1 interrupt
; No, done ; Reset hours to 1 ; Done
TABLE 12-2:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Bit 7
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
GIE/GIEH PEIE/GIEL PSPIF
(1)
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
ADIF ADIE ADIP
PSPIE(1) PSPIP(1)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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13.0
* * * * * * *
TIMER2 MODULE
13.1
Timer2 Operation
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 SSP module optional use of TMR2 output to generate clock shift
Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
Timer2 has a control register shown in Register 13-1. TMR2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2 are controlled by this register.
REGISTER 13-1:
T2CON: TIMER2 CONTROL REGISTER
U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 T2CKPS0 bit 0 TMR2ON T2CKPS1
bit 7 bit 6-3
Unimplemented: Read as `0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale * * * 1111 = 1:16 postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
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13.2 Timer2 Interrupt 13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output(1) Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS1:T2CKPS0
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4
TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 13-1:
Name INTCON PIR1 PIE1 IPR1 TMR2 T2CON PR2 OSCCON Legend: Note 1: Bit 7
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) -- IDLEN ADIF ADIE ADIP
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Timer2 Module Register Timer2 Period Register IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 0000 qq00 0000 qq00
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
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14.0 TIMER3 MODULE
Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 Oscillator Enable bit (T1OSCEN) which can be a clock source for Timer3. The Timer3 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from CCP module trigger
REGISTER 14-1:
T3CON: TIMER3 CONTROL REGISTER
R/W-0 RD16 bit 7 R/W-0 T3CCP2 R/W-0 T3CKPS1 R/W-0 T3CKPS0 R/W-0 T3CCP1 R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the clock source for compare/capture CCP modules 01 = Timer3 is the clock source for compare/capture of CCP2, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP modules T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6, 3
bit 5-4
bit 2
bit 1
bit 0
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14.1 Timer3 Operation
Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC1:TRISC0 value is ignored and the pins are read as `0'. Timer3 also has an internal "Reset input". This Reset can be generated by the CCP module (see Section 15.4.4 "Special Event Trigger").
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
TMR3IF Overflow Interrupt Flag bit TMR3H CCP Special Event Trigger T3CCPx CLR TMR3L 1 TMR3ON On/Off T3SYNC 0 Synchronized Clock Input
T1OSO/ T1CKI
T1OSC 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 0 2 TMR3CS T3CKPS1:T3CKPS0 Peripheral Clocks Synchronize det
T1OSI
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
8 TMR3H 8 8
Data Bus<7:0>
Write TMR3L Read TMR3L Set TMR3IF Flag bit on Overflow 8 Timer3 High Byte TMR3 TMR3L CLR CCP Special Event Trigger T3CCPx Synchronized 0 Clock Input 1 To Timer1 Clock Input T1OSO/ T1CKI T1OSC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 0 2 Peripheral Clocks T3CKPS1:T3CKPS0 TMR3CS TMR3ON On/Off T3SYNC Synchronize det
T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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14.2 Timer1 Oscillator 14.4
The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See Section 12.2 "Timer1 Oscillator" for further details.
Resetting Timer3 Using a CCP Trigger Output
If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 "Special Event Trigger" for more information. Note: The special event triggers from the CCP module will not set interrupt flag bit, TMR3IF (PIR1<0>).
14.3
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 Interrupt Enable bit, TMR3IE (PIE2<1>).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3.
TABLE 14-1:
Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Bit 7 GIE/ GIEH OSCIF OSCIE OSCIP
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 6 PEIE/ GIEL CMIF CMIE CMIP Bit 5 TMR0IE -- -- -- Bit 4 INT0IE EEIF EEIE EEIP Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF CCP2IF CCP2IE CCP2IP Value on POR, BOR Value on all other Resets
0000 000x 0000 000u 00-0 0000 00-0 0000 00-0 0000 00-0 0000 11-1 1111 11-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 RD16 T1RUN T3CCP2 T1CKPS1 T1CKPS0 T1OSCEN T3CKPS1 T3CKPS0 T3CCP1 T1SYNC T3SYNC
TMR1CS TMR1ON 0000 0000 u0uu uuuu TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module.
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15.0 CAPTURE/COMPARE/PWM (CCP) MODULES
Note: In 28-pin devices, both CCP1 and CCP2 function as standard CCP modules. In 40-pin devices, CCP1 is implemented as an Enhanced CCP module, offering additional capabilities in PWM mode. Capture and Compare modes are identical in all modules regardless of the device. Please see Section 16.0 "Enhanced Capture/Compare/PWM (ECCP) Module" for a discussion of the enhanced PWM capabilities of the CCP1 module.
The standard CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. Table 15-1 shows the timer resources required for each of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module is described with respect to CCP1 except where noted. Table 15-2 shows the interaction of the CCP modules.
REGISTER 15-1:
CCPxCON: CCP MODULE CONTROL REGISTER
U-0 -- bit 7 U-0 -- R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
bit 7-6 bit 5-4
Reserved: Read as `0'. See Section 16.0 "Enhanced Capture/Compare/PWM (ECCP) Module". DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP pin Low; on compare match, force CCP pin High (CCPxIF bit is set) 1001 = Compare mode, initialize CCP pin High; on compare match, force CCP pin Low (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on compare match (CCPxIF bit is set, CCP pin operates as a port pin for input and output) 1011 = Compare mode, trigger special event (CCP2IF bit is set) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
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15.1 CCP1 Module 15.2 CCP2 Module
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. CCP2 functions identically to CCP1 except for the enhanced PWM modes offered by CCP2
TABLE 15-1:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2
CCP Mode Capture Compare PWM
TABLE 15-2:
Capture Capture Compare PWM PWM PWM
INTERACTION OF TWO CCP MODULES
Interaction TMR1 or TMR3 time base. Time base can be different for each CCP. The compare could be configured for the special event trigger which clears either TMR1 or TMR3 depending upon which time base is used. The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3 depending upon which time base is used. The PWMs will have the same frequency and update rate (TMR2 interrupt). None. None. Capture Compare Compare PWM Capture Compare
CCPx Mode CCPy Mode
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15.3 Capture Mode
15.3.3 SOFTWARE INTERRUPT
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1/P1A. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode.
15.3.4
CCP PRESCALER
The event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
There are four prescaler settings specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
15.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1/P1A pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1/P1A is configured as an output, a write to the port can cause a capture condition.
EXAMPLE 15-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value
15.3.2
TIMER1/TIMER3 MODE SELECTION
CCP1CON, F NEW_CAPT_PS
The timers that are to be used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register.
MOVWF
CCP1CON
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H Set Flag bit CCP1IF Prescaler / 1, 4, 16 T3CCP2 TMR3 Enable CCPR1H and Edge Detect CCP1CON<3:0> Q's Set Flag bit CCP2IF T3CCP1 T3CCP2 Prescaler / 1, 4, 16 TMR3H TMR3 Enable CCPR2H and Edge Detect CCP2CON<3:0> Q's TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L CCPR2L TMR3L TMR1 Enable TMR1H TMR1L CCPR1L TMR3L
CCP1 pin
T3CCP2
CCP2 pin
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15.4 Compare Mode
15.4.2 TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1/P1A (RC1/T1OSI/CCP2) pin: * * * * Is driven High Is driven Low Toggles output (High to Low or Low to High) Remains unchanged (interrupt only) Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
15.4.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
The action on the pin is based on the value of control bits, CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag bit, CCP1IF (CCP2IF), is set.
15.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP2 resets either the TMR1 or TMR3 register pair. Additionally, the CCP2 special event trigger will start an A/D conversion if the A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits.
15.4.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by clearing the appropriate TRISC bit. Note: Clearing the CCP1CON register will force the RC2/CCP1/P1A compare output latch to the default low level. This is not the PORTC I/O data latch.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will: Reset Timer1 or Timer3 but not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only)
Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RC2/CCP1/P1A pin TRISC<2> Output Enable S R Output Logic Comparator
Match T3CCP2
CCP1CON<3:0> Mode Select
0
1
TMR1H Special Event Trigger
TMR1L
TMR3H
TMR3L
Set Flag bit CCP2IF
T3CCP1 T3CCP2
0
1
Q RC1/T1OSI/CCP2 pin TRISC<1> Output Enable
S R
Output Logic
Comparator Match CCPR2H CCPR2L
CCP2CON<3:0> Mode Select
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TABLE 15-3:
Name INTCON PIR1 PIE1 IPR1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON PIR2 PIE2 IPR2 TMR3L TMR3H T3CON
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF Value on POR, BOR Value on all other Resets
Bit 7
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) ADIF ADIE ADIP
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 T1RUN Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- DC1B1 DC1B0 CCP1M3 Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- OSCFIF OSCFIE OSCFIP -- CMIF CMIE CMIP DC2B1 -- -- -- DC2B0 EEIF EEIE EEIP CCP2M3 BCLIF BCLIE BCLIP LVDIF LVDIE LVDIP TMR3IF TMR3IE TMR3IP CCP2IF
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 00-0 0000 00-0 0000 CCP2IE 00-0 0000 00-0 0000 CCP2IP 11-1 1111 11-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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15.5 PWM Mode
15.5.1 PWM PERIOD
In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation.
EQUATION 15-1:
PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 15-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.5.3 "Setup for PWM Operation".
FIGURE 15-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H (Slave)
15.5.2
Q RC2/CCP1/P1A
PWM DUTY CYCLE
Comparator
R
TMR2
(Note 1) S
Comparator Clear Timer, CCP1 pin and latch D.C.
TRISC<2>
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation.
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.
PR2
Note: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base.
A PWM output (Figure 15-4) has a time base (period) and a time that the output is high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 15-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
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The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation.
15.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and the CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
EQUATION 15-3:
log FOSC FPWM bits PWM Resolution (max) = log(2)
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 15-5:
Name INTCON PIR1 PIE1 IPR1 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON OSCCON
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
Bit 7
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) ADIF ADIE ADIP
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
PORTC Data Direction Register Timer2 Module Register Timer2 Module Period Register -- Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- IDLEN -- IRCF2 DC2B1 IRCF1 DC2B0 IRCF0 CCP2M3 OSTS CCP2M2 IOFS CCP2M1 SCS1 SCS0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 --00 0000 --00 0000 0000 qq00 0000 qq00
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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NOTES:
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16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE
The ECCP (Enhanced Capture/ Compare/ PWM) module is only available on PIC18F4X20 devices. The ECCP module differs from the CCP with the addition of an enhanced PWM mode which allows for 2 or 4 output channels, user-selectable polarity, dead band control and automatic shutdown and restart. These features are discussed in detail in Section 16.4 "Enhanced PWM Mode". The control register for CCP1 is shown in Register 16-1. It differs from the CCP1CON register of PIC18F2X20 devices in that the two Most Significant bits are implemented to control enhanced PWM functionality.
Note:
In 40 and 44-pin devices, the CCP1 module is implemented as a standard CCP module with enhanced PWM capabilities. Operation of the Capture, Compare and standard single output PWM modes is described in Section 15.0 "Capture/Compare/PWM (CCP) Modules". Discussion in that section relating to PWM frequency and duty cycle also apply to the enhanced PWM mode.
REGISTER 16-1:
CCP1CON REGISTER FOR ENHANCED CCP OPERATION (PIC18F4X20 ONLY)
R/W-0 P1M1 bit 7 R/W-0 P1M0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
bit 7-6
bit 5-4
bit 3-0
P1M1:P1M0: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10 (Capture, Compare, or disabled): xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11 (PWM modes): 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with dead band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive DC1B1:DC1B0: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M3:CCP1M0: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin operates as a port pin for input and output) 1011 = Compare mode, trigger special event (ECCP1IF bit is set, ECCP resets TMR1or TMR2 and starts an A/D conversion if the A/D module is enabled) 1100 = PWM mode, P1A, P1C active-high, P1B, P1D active-high 1101 = PWM mode, P1A, P1C active-high, P1B, P1D active-low 1110 = PWM mode, P1A, P1C active-low, P1B, P1D active-high 1111 = PWM mode, P1A, P1C active-low, P1B, P1D active-low Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional registers associated with enhanced PWM operation and Auto-Shutdown features: * PWM1CON * ECCPAS All other registers associated with the ECCP module are identical to those used for the CCP1 module in PIC18F2X20 devices, including register and individual bit names. Likewise, the timer assignments and interactions between the two CCP modules are identical, regardless of whether CCP1 is a standard or enhanced module.
16.2
Capture and Compare Modes
The Capture and Compare modes of the ECCP module are identical in operation to that of CCP1, as discussed in Section 15.3 "Capture Mode" and Section 15.4 "Compare Mode". No changes are required when moving between these modules on PIC18F2X20 and PIC18F4X20 devices.
16.3
Standard PWM Mode
When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode, as described in Section 15.4 "Compare Mode". Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 15.5.3 "Setup for PWM Operation" or Section 16.4.7 "Setup for PWM Operation". The latter is more generic but will work for either single or multi output PWM.
16.1
ECCP Outputs
The Enhanced CCP module may have up to four outputs depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC and PORTD. The pin assignments are summarized in Table 16-1. To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mn and CCP1Mn bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs.
TABLE 16-1:
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
CCP1CON Configuration 00xx11xx 10xx11xx x1xx11xx RC2 CCP1 P1A P1A RD5 RD5/PSP5 P1B P1B RD6 RD6/PSP6 RD6/PSP6 P1C RD7 RD7/PSP7 RD6/PSP6 P1D
ECCP Mode Compatible CCP Dual PWM Quad PWM
Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: TRIS register values must be configured appropriately. 2: With ECCP in Dual or Quad PWM mode, the PSP input/output control of PORTD is overridden by P1B, P1C and P1D.
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16.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits of the CCP1CON register (CCP1CON<7:6> and CCP1CON<3:0>, respectively). Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRISD bits for output.
16.4.1
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode discussed in Section 15.5 "PWM Mode". The HalfBridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 16-2.
FIGURE 16-1:
Duty Cycle Registers CCPR1L
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4> P1M1<1:0> 2 CCP1M<3:0> 4
CCP1/P1A TRISD<4> CCPR1H (Slave) P1B R Q Output Controller P1C TMR2 (Note 1) S P1D Clear Timer, set CCP1 pin and latch D.C. PWM1CON TRISD<7> TRISD<6> TRISD<5>
RC2/CCP1/P1A
RD5/PSP5/P1B
Comparator
RD6/PSP6/P1C
Comparator
RD7/PSP7/P1D
PR2
Note:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.
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FIGURE 16-2:
CCP1CON <7:6>
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0 SIGNAL Duty Cycle Period P1A Modulated Delay(1) P1A Modulated Delay(1) PR2+1
00
(Single Output)
10
(Half-Bridge)
P1B Modulated P1A Active
01
(Full-Bridge, Forward)
P1B Inactive P1C Inactive P1D Modulated P1A Inactive
11
(Full-Bridge, Reverse)
P1B Modulated P1C Active P1D Inactive
FIGURE 16-3:
CCP1CON <7:6>
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0 SIGNAL Duty Cycle Period P1A Modulated P1A Modulated PR2+1
00
(Single Output)
10
(Half-Bridge)
Delay(1) P1B Modulated P1A Active
Delay(1)
01
(Full-Bridge, Forward)
P1B Inactive P1C Inactive P1D Modulated P1A Inactive
11
(Full-Bridge, Reverse)
P1B Modulated P1C Active P1D Inactive
Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead band delay is programmed using the PWM1CON register (see Section 16.4.4 "Programmable Dead Band Delay").
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16.4.2 HALF-BRIDGE MODE FIGURE 16-4:
Period Duty Cycle P1A(2) td P1B(2)
(1)
In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RC2/CCP1/P1A pin, while the complementary PWM output signal is output on the RD5/ PSP5/P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable dead band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 16.4.4 "Programmable Dead Band Delay" for more details of the dead band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs.
HALF-BRIDGE PWM OUTPUT
Period
td
(1)
(1)
td = Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high.
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull") PIC18F4220/4320 P1A FET Driver
+ V Load
FET Driver P1B
+ V -
Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F4220/4320 FET Driver P1A
V-
FET Driver
FET Driver P1B
Load
FET Driver
V-
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16.4.3 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RC2/CCP1/P1A is continuously active and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continuously active and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-6. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<5:7> data latches. The TRISC<2> and TRISD<5:7> bits must be cleared to make the P1A, P1B, P1C and P1D pins output.
FIGURE 16-6:
FULL-BRIDGE PWM OUTPUT
FORWARD MODE Period P1A(2) Duty Cycle P1B(2)
P1C(2)
P1D(2) (1) REVERSE MODE Period Duty Cycle P1A(2) P1B(2) P1C(2) (1)
P1D(2) (1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high.
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FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F4220/4320 P1A
FET Driver
QA
QC
FET Driver
P1B FET Driver
Load FET Driver
P1C
QB
QD
VP1D
16.4.3.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of 4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 16-8. Note that in the Full-Bridge Output mode, the ECCP module does not provide any dead band delay. In general, since only one output is modulated at all times, dead band delay is not required. However, there is a situation where a dead band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time.
Figure 16-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 16-7) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on.
Other options to prevent shoot-through current may exist.
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FIGURE 16-8:
SIGNAL
PWM DIRECTION CHANGE
Period(1) Period
P1A (Active High) P1B (Active High) DC P1C (Active High) P1D (Active High) DC (Note 2)
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time.
FIGURE 16-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1)
Forward Period t1 Reverse Period
P1A P1B P1C P1D DC
DC ton(2)
External Switch C toff(3) External Switch D Potential Shoot-Through Current t = toff - ton(2,3)
Note 1: All signals are shown as active-high. 2: ton is the turn-on delay of power switch QC and its driver. 3: toff is the turn-off delay of power switch QD and its driver.
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16.4.4 PROGRAMMABLE DEAD BAND DELAY
In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead band delay is available to avoid shootthrough current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 16-4 for illustration. The lower seven bits of the PWM1CON register (Register 16-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). A shutdown event can be caused by either of the two comparator modules or the INT0 pin (or any combination of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the INT0 pin can also trigger a shutdown. The autoshutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (ECCPAS<6:4>). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/ P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCPASE bit (ECCPAS<7>) is also set to hold the enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active.
16.4.5
ENHANCED PWM AUTO-SHUTDOWN
When the ECCP is programmed for any of the enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the enhanced PWM output pins into a defined shutdown state when a shutdown event occurs.
REGISTER 16-2:
PWM1CON: PWM CONFIGURATION REGISTER
R/W-0 PRSEN bit 7 R/W-0 PDC6 R/W-0 PDC5 R/W-0 PDC4 R/W-0 PDC3 R/W-0 PDC2 R/W-0 PDC1 R/W-0 PDC0 bit 0
bit 7
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM PDC<6:0>: PWM Delay Count bits Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-0
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REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER
R/W-0 bit 7 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = INT0 101 = INT0 or Comparator 1 110 = INT0 or Comparator 2 111 = INT0 or Comparator 1 or Comparator 2 PSSAC<1:0>: Pin A and C Shutdown State Control bits 00 = Drive Pins A and C to `0' 01 = Drive Pins A and C to `1' 1x = Pins A and C tri-state PSSBD<1:0>: Pin B and D Shutdown State Control bits 00 = Drive Pins B and D to `0' 01 = Drive Pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 bit 0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
bit 6-4
bit 3-2
bit 1-0
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16.4.5.1 Auto-Shutdown and Automatic Restart 16.4.6 START-UP CONSIDERATIONS
The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared. If PRSEN = 0 (Figure 16-11), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins.
Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCPASE bit.
FIGURE 16-10:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period PWM Period PWM Period
PWM Activity Dead Time Duty Cycle Shutdown Event Dead Time Duty Cycle Dead Time Duty Cycle
ECCPASE bit
FIGURE 16-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period PWM Period PWM Period
PWM Activity Dead Time Duty Cycle Shutdown Event Dead Time Duty Cycle Dead Time Duty Cycle
ECCPASE bit ECCPASE Cleared by Firmware
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16.4.7 SETUP FOR PWM OPERATION 16.4.8
The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISC and TRISD bits. Set the PWM period by loading the PR2 register. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M1:P1M0 bits. * Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. For Half-Bridge Output mode, set the dead band delay by loading PWM1CON<6:0> with the appropriate value. If auto-shutdown operation is required, load the ECCPAS register: * Select the auto-shutdown sources using the ECCPAS<2:0> bits. * Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. * Set the ECCPASE bit (ECCPAS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. If auto-restart operation is required, set the PRSEN bit (PWM1CON<7>). Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). Enable PWM outputs after a new PWM cycle has started: * Wait until TMR2 overflows (TMR2IF bit is set). * Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISC and TRISD bits. * Clear the ECCPASE bit (ECCPAS<7>).
OPERATION IN POWER MANAGED MODES
2. 3.
In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other power managed modes, the selected power managed mode clock will clock Timer2. Other power managed mode clocks will most likely be different than the primary clock frequency.
4. 5.
16.4.8.1
OPERATION WITH FAIL-SAFE CLOCK MONITOR
6.
If the Fail-Safe Clock Monitor is enabled (CONFIG1H<6> is programmed), a clock failure will force the device into the RC_RUN Power Managed mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the internal oscillator clock source which may have a different clock frequency than the primary clock. By loading the IRCF2:IRCF0 bits on Resets, the user can obtain a frequency higher than the default INTRC clock source in the event of a clock failure. See the previous section for additional details.
16.4.9
EFFECTS OF A RESET
7. 8.
Both Power-on and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module.
9.
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TABLE 16-2:
Name INTCON RCON PIR1 PIE1 IPR1 TMR2 PR2 T2CON TRISC TRISD CCPR1H CCPR1L CCP1CON ECCPAS PWM1CON OSCCON Legend:
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Bit 6 Bit 5 TMR0IE -- RCIF RCIE RCIP Bit 4 INT0IE RI TXIF TXIE TXIP Bit 3 RBIE TO SSPIF SSPIE SSPIP Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP Bit 0 RBIF BOR Value on POR, BOR Value on all other Resets
Bit 7
GIE/GIEH PEIE/GIEL IPEN PSPIF PSPIE PSPIP -- ADIF ADIE ADIP
0000 000x 0000 000u 0--1 11qq 0--q qquu
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Module Register Timer2 Module Period Register -- TOUTPS3 PORTC Data Direction Register PORTD Data Direction Register Enhanced Capture/Compare/PWM Register 1 High Byte Enhanced Capture/Compare/PWM Register 1 Low Byte P1M1 PRSEN IDLEN P1M0 PDC6 IRCF2 DC1B1 PDC5 IRCF1 DC1B0 PDC4 IRCF0 CCP1M3 PSSAC1 PDC3 OSTS CCP1M2 PSSAC0 PDC2 IOFS CCP1M1 PSSBD1 PDC1 SCS1 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 PSSBD0 0000 0000 0000 0000 PDC0 SCS0 0000 0000 0000 0000 0000 q000 0000 q000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the ECCP module in enhanced PWM mode.
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NOTES:
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17.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
Master SSP (MSSP) Module Overview 17.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/AN4/SS/LVDIN/C2OUT Register 17-1 shows the block diagram of the MSSP module when operating in SPI mode.
17.1
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
17.2
Control Registers
SSPSR reg RC4/SDI/SDA bit 0 Shift Clock
The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections.
RC5/SDO
SS Control Enable RA5/AN4/SS/ LVDIN/C2OUT Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64
(
)
RC3/SCK/ SCL
Data to TX/RX in SSPSR TRIS bit
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17.3.1 REGISTERS
The MSSP module has four registers for SPI mode operation. These are: * * * * MSSP Control Register 1 (SSPCON1) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.
REGISTER 17-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 7
SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. CKE: SPI Clock Edge Select bit When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit Used in I2C mode only. P: Stop bit Used in I2C mode only. S: Start bit Used in I2C mode only. R/W: Read/Write bit information Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
bit 6
bit 5
SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When the MSSP is enabled in SPI mode, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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17.3.2 OPERATION
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a Transmit/Receive Shift register (SSPSR) and a Buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the Buffer Full Detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the * * * * SSPBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions.
EXAMPLE 17-1:
LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT, BF LOOP SSPBUF, W RXDATA TXDATA, W SSPBUF ;Has data been received(transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
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17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI must have TRISC<4> bit set * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISC<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Register 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb SDO SDI
SPI Slave SSPM3:SSPM0 = 010xb
Serial Input Buffer (SSPBUF)
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO
Shift Register (SSPSR) MSb LSb
SCK PROCESSOR 1
Serial Clock
SCK PROCESSOR 2
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17.3.5 MASTER MODE
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 17-3, Figure 17-5 and Figure 17-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) (Timer2 output)/2
The maximum data rate is approximately 3.0 Mbps, limited by timing requirements (see Table 26-14 through Table 26-17). Figure 17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
FIGURE 17-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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17.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in power managed modes, the slave can transmit/receive data. When a byte is received, the device will wake-up from power managed modes. is tri-stated, even if in the middle of a transmitted byte. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset when the SS pin is set high. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, SSPSR is cleared. This can be done by either driving the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict.
17.3.7
SLAVE SELECT CONTROL
The SS pin allows a master controller to select one of several slave controllers for communications in systems with more than one slave. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The SS pin is configured for input by setting TRISA<5>. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SDO
bit 7
bit 6
bit 7
bit 0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit 0 bit 7 bit 7
Next Q4 Cycle after Q2
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FIGURE 17-5:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit 7
bit 0
Next Q4 Cycle after Q2
FIGURE 17-6:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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17.3.8 MASTER IN POWER MANAGED MODES 17.3.8.1 Slave in Power Managed Modes
In Master mode, module clocks may be operating at a different speed than when in full power mode, or in the case of the Sleep Power Managed mode, all clocks are halted. In most power managed modes, a clock is provided to the peripherals and is derived from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the internal oscillator block (one of eight frequencies between 31 kHz and 8 MHz). See Section 2.7 "Clock Sources and Oscillator Switching" for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from a power managed mode when the master completes sending data. If an exit from a power managed mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will pause until the device wakes from the power managed mode. After the device returns to full power mode, the module will resume transmitting and receiving data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if MSSP interrupts are enabled, will wake the device from a power managed mode.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the current transfer.
17.3.10
BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
TABLE 17-1:
SPI BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1
There is also an SMP bit which controls when the data is sampled.
TABLE 17-2:
Name INTCON PIR1 PIE1 IPR1 TRISC SSPBUF SSPCON1 TRISA SSPSTAT
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other Resets
GIE/GIEH PSPIF(1) PSPIE(1) PSPIP(1)
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx uuuu uuuu
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL TRISA7(1) SMP SSPOV TRISA6(1) CKE SSPEN D/A CKP P SSPM3 S SSPM2 R/W SSPM1 UA SSPM0 BF PORTA Data Direction Register
0000 0000 0000 0000 --11 1111 --11 1111 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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17.4 I2C Mode
17.4.1 REGISTERS
The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial Clock (SCL) - RC3/SCK/SCL * Serial Data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs using the TRISC<4:3> bits. The MSSP module has six registers for I2C operation. These are: * * * * * MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
Addr Match
FIGURE 17-7:
MSSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write
RC3/SCK/ SCL
RC4/SDI/ SDA
MSb
LSb
Match Detect
SSPADD reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT reg)
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
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REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled 0 = Slew rate control enabled CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset when SSPEN is cleared or a Start bit has been detected. S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset when SSPEN is cleared or a Stop bit has been detected. R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: OR'ing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty In Receive mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR
2003 Microchip Technology Inc.
R/W-0 CKE
R-0 D/A
R-0 P
R-0 S
R-0 R/W
R-0 UA
R-0 BF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be configured as input pins.
bit 6
bit 5
bit 4
CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved, or implemented in SPI mode only.
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: bit 4 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0
bit 6
bit 5
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle
bit 3
bit 2
bit 1
RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is disabled Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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17.4.2 OPERATION 17.4.3.1 Addressing
The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse.
Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits. When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared by software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101.
In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
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17.4.3.2 Reception 17.4.3.3 Transmission
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set. An MSSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 "Clock Stretching" for more detail. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 17.4.4 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 17-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.
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FIGURE 17-8:
DS39599C-page 170
Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
PIC18F2220/2320/4220/4320
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
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CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 17-9:
2003 Microchip Technology Inc.
R/W = 1 ACK D1 D0 D4 D3 D5 D7 D6 D2 A1 D3 D2 ACK D5 D4 D7 D6 Transmitting Data Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software From SSPIF ISR SSPBUF is written in software SSPBUF is written in software Cleared in software From SSPIF ISR CKP is set in software CKP is set in software
Receiving Address
SDA
A7
A6
A5
SCL
1
2
3
S
Data in sampled
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
PIC18F2220/2320/4220/4320
CKP
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FIGURE 17-10:
DS39599C-page 172
Clock is held low until update of SSPADD has taken place R/W = 0 A8 ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPADD has taken place 0 A9 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address
Receive First Byte of Address
SDA
1
1
1
1
SCL
S
1
2
3
4
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
PIC18F2220/2320/4220/4320
SSPOV (SSPCON1<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
2003 Microchip Technology Inc.
CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 17-11:
Bus master terminates transfer Clock is held low until CKP is set to `1' R/W = 1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK
2003 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. CKP is set in software CKP is automatically cleared in hardware holding SCL low
Receive First Byte of Address
SDA
1
1
1
SCL
S
1
2
3
SSPIF
(PIR1<3>)
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
PIC18F2220/2320/4220/4320
CKP (SSPCON1<4>)
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17.4.4 CLOCK STRETCHING 17.4.4.3
Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence.
Clock Stretching for 7-bit Slave Transmit Mode
7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 17-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit.
17.4.4.1
Clock Stretching for 7-bit Slave Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 17-13). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition.
17.4.4.4
Clock Stretching for 10-bit Slave Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the high order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 17-11).
17.4.4.2
Clock Stretching for 10-bit Slave Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but the CKP bit is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.
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17.4.4.5 Clock Synchronization and the CKP bit (SEN = 1)
The SEN bit is also used to synchronize writes to the CKP bit. If a user clears the CKP bit, the SCL output is forced to `0'. When the SEN bit is set to `1', setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12). Note: If the SEN bit is `0', clearing the CKP bit will result in immediately driving the SCL output to `0' regardless of the current state.
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device asserts clock Master device deasserts clock
WR SSPCON1
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FIGURE 17-13:
DS39599C-page 176
Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
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BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
CKP CKP written to `1' in software BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
2003 Microchip Technology Inc.
If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur
FIGURE 17-14:
Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D7 D6 D5 D4 D0 ACK D3 D2 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte
Clock is held low until update of SSPADD has taken place
Clock is not held low because ACK = 1 ACK D1 D0
Receive First Byte of Address A9 A8
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6 1 2 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPADD needs to be updated Note: Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock. An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. CKP written to `1' in software
SDA
1
1
1
1
0
SCL
S
1
2
3
4
5
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
SSPOV (SSPCON1<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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CKP
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17.4.5 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15).
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE)
Address is compared to general call address after ACK, set interrupt R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK
SDA SCL S SSPIF BF (SSPSTAT<0>) 1
General Call Address
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) `0'
GCEN (SSPCON2<7>)
`1'
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17.4.6 MASTER MODE
Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDA and SCL. Assert a Repeated Start condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDA and SCL. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt if enabled): * * * * * Start Condition Stop Condition Data Transfer Byte Transmitted/Received Acknowledge Transmit Repeated Start
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS39599C-page 179 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0>
SDA SDA In
SCL
SCL In Bus Collision
Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2)
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Clock Cntl
Start bit, Stop bit, Acknowledge Generate
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17.4.6.1 I2C Master Mode Operation
A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 17.4.7 "Baud Rate" for more detail.
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17.4.7
2
BAUD RATE
17.4.7.1
In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to `0' and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 17-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD.
Baud Rate Generation in Power Managed Modes
When the device is operating in a power managed mode, the clock source to the Baud Rate Generator may change frequency or stop, depending on the power managed mode and clock source selected. In most power modes, the Baud Rate Generator continues to be clocked but may be clocked from the primary clock (selected in a configuration word), the secondary clock (Timer1 oscillator at 32.768 kHz) or the internal oscillator block (one of eight frequencies between 31 kHz and 8 MHz). If the Sleep mode is selected, all clocks are stopped and the Baud Rate Generator will not be clocked.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0 SSPADD<6:0>
SSPM3:SSPM0 SCL
Reload Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 17-3:
FOSC 40 MHz 40 MHz 40 MHz 16 MHz 16 MHz 16 MHz 4 MHz 4 MHz 4 MHz Note 1: 2:
I2C CLOCK RATE W/BRG
FCY 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz I2C FCY*2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz I2C SSPADD VALUE (See Register 17-4, Mode 1000) 18h 1Fh 63h 09h 0Bh 27h 02h 09h 00h FSCL(2) (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100kHz 1 MHz(1)
The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 "Clock Arbitration").
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17.4.7.2 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 17-18).
FIGURE 17-18:
SDA
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX DX-1 SCL allowed to transition high
SCL deasserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off)
03h
02h
SCL is sampled high, reload takes place and BRG starts its count BRG Reload
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17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 WCOL Status Flag
To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of Start bit, hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit SDA TBRG 2nd bit
Write to SEN bit occurs here
TBRG
SCL S
TBRG
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17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL (no change). SDA = 1, SCL = 1 At completion of Start bit, hardware clears RSEN bit and sets SSPIF TBRG 1st bit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated Start
TBRG SDA Falling edge of ninth clock, end of Xmit SCL
TBRG
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17.4.10 I2C MASTER MODE TRANSMISSION 17.4.10.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full Flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter #107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit, during the ninth bit time, if an address match occurred or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 17-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data.
17.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2<3>). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state, awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>).
17.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read.
17.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception.
17.4.11.3
WCOL Status Flag
17.4.10.1
BF Status Flag
If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out.
17.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software.
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FIGURE 17-21:
DS39599C-page 186
Write SSPCON2<0> SEN = 1, Start condition begins From slave, clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0 ACK SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W, start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 SSPIF Cleared in software Cleared in software service routine from SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After Start condition, SEN cleared by hardware SSPBUF is written in software PEN
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I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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R/W
FIGURE 17-22:
Write to SSPCON2<4> to start Acknowledge sequence, SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1, start next receive RCEN cleared automatically ACK from master, SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence, SDA = ACKDT = 1 PEN bit = 1 written here
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A1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK is not sent Bus master terminates transfer
Write to SSPCON2<0> (SEN = 1), begin Start condition
SEN = 0 Write to SSPBUF occurs here, start XMIT
Transmit Address to Slave
SDA
A7
A6 A5 A4 A3 A2
SCL
S
Set SSPIF interrupt at end of receive
1 5 1 2 3 4 5 6 7 8 1 2 3 4
2
3 4 8 9
6
7 9
5
6
7
8
9
Set SSPIF at end of receive
P
Set SSPIF interrupt at end of Acknowledge sequence
Data shifted in on falling edge of CLK
SSPIF
Cleared in software Cleared in software
Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software
SDA = 0, SCL = 1, while CPU responds to SSPIF
Cleared in software
Set P bit (SSPSTAT<4>) and SSPIF
BF (SSPSTAT<0>)
Last bit is shifted into SSPSR and contents are unloaded into SSPBUF
SSPOV
SSPOV is set because SSPBUF is still full
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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ACKEN
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17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 17-23). A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 17-24).
17.4.13.1 17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, write to SSPCON2, ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared
SCL
8
9
SSPIF Cleared in software Set SSPIF at the end of Acknowledge sequence
Set SSPIF at the end of receive
Cleared in software
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2, set PEN Falling edge of 9th clock TBRG SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set
SCL
SDA
ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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17.4.14 POWER MANAGED MODE OPERATION 17.4.17
While in any power managed mode, the I2C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled).
MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION
17.4.15
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the current transfer.
17.4.16
MULTI-MASTER MODE
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the I2C port to its Idle state (Figure 17-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared.
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred.
SDA
SCL
Set Bus Collision Interrupt Flag (BCLIF)
BCLIF
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17.4.17.1 Bus Collision During a Start Condition
During a Start condition, a bus collision occurs if: a) b) SDA or SCL is sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0 and during this time, if the SCL pins are sampled as `0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions.
During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low or the SCL pin is already low, then all of the following occur: * The Start condition is aborted * The BCLIF flag is set * The MSSP module is reset to its Idle state (Figure 17-26) The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1.
SDA
SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SEN cleared automatically because of bus collision. SSP module reset into Idle state.
BCLIF
SSPIF
SSPIF and BCLIF are cleared in software
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FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1 TBRG SDA TBRG
SCL
Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
SEN
BCLIF Interrupt cleared in software S SSPIF `0' `0' `0' `0'
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF
SDA
SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG Time-out Set SEN, enable Start sequence if SDA = 1, SCL = 1
SCL
SEN
BCLIF
`0'
S
SSPIF SDA = 0, SCL = 1, set SSPIF Interrupts cleared in software
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17.4.17.2 Bus Collision During a Repeated Start Condition
During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 17-30). If at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete.
When the user deasserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled.
FIGURE 17-29:
SDA
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software `0' `0'
S SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF `0'
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17.4.17.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 17-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 17-32).
b)
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF
SDA SDA asserted low SCL PEN BCLIF P SSPIF `0' `0'
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA Assert SDA SCL PEN BCLIF P SSPIF `0' `0' SCL goes low before SDA goes high, set BCLIF
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NOTES:
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18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
18.1 Asynchronous Operation in Power Managed Modes
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules available in the PIC18F2X20/4X20 family of microcontrollers. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The USART can be configured in the following modes: * Asynchronous (full-duplex) * Synchronous - Master (half-duplex) * Synchronous - Slave (half-duplex) The RC6/TX/CK and RC7/RX/DT pins must be configured as shown for use with the Universal Synchronous Asynchronous Receiver Transmitter: * SPEN (RCSTA<7>) bit must be set (= 1) * TRISC<7> bit must be set (= 1) * TRISC<6> bit must be cleared (= 0) Register 18-1 shows the Transmit Status and Control register (TXSTA) and Register 18-2 shows the Receive Status and Control register (RCSTA).
The USART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This mode makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6 "INTOSC Frequency Drift" for more information). The other method adjusts the value in the Baud Rate Generator since there may be not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.
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REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 CSRC bit 7 bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2
bit 1
bit 0
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REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 SPEN bit 7 bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enable address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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18.2 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free-running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 18-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 18-1. From this, the error in baud rate can be determined. Example 18-1 shows the calculation of the baud rate error for the following conditions: * * * * FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks, because the FOSC/(16 (X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
18.2.1
POWER MANAGED MODE OPERATION
The system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode, no clocks are present and in PRI_IDLE, the primary clock source continues to provide clocks to the baud rate generator; however, in other power managed modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted.
18.2.2
SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
EXAMPLE 18-1:
Desired Baud Rate Solving for X: X X X
CALCULATING BAUD RATE ERROR
= FOSC/(64 (X + 1)) = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error Desired Baud Rate = (9615 - 9600)/9600 = 0.16% = (Calculated Baud Rate - Desired Baud Rate)
TABLE 18-1:
SYNC
BAUD RATE FORMULA
BRGH = 0 (Low Speed) Baud Rate = FOSC/(64 (X + 1)) Baud Rate = FOSC/(4 (X + 1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16 (X + 1)) N/A
0 (Asynchronous) 1 (Synchronous)
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2:
Name TXSTA RCSTA SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR, BOR 0000 -010 0000 -00x 0000 0000 Value on all other Resets 0000 -010 0000 -00x 0000 0000
Bit 7 CSRC SPEN
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 18-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0, LOW SPEED)
FOSC = 20.000 MHz Actual Rate (K) -- 1.22 2.40 9.47 19.53 39.06 62.50 78.13 104.17 -- -- 312.50 -- % Error -- 1.73 0.16 -1.36 1.73 1.73 8.51 1.73 8.51 -- -- 4.17 -- 0 -- SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 2.44 9.62 18.94 39.06 56.82 78.13 89.29 125.00 208.33 312.50 625.00 % Error -- -- 1.73 0.16 -1.36 1.73 -1.36 1.73 -6.99 8.51 -16.67 4.17 0.00 SPBRG value
(decimal)
FOSC = 16.000 MHz Actual Rate (K) 0.98 1.20 2.40 9.62 19.23 35.71 62.50 83.33 -- 125.00 250.00 -- -- % Error 225.52 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 -- 8.51 0.00 -- -- SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.61 1.20 2.40 9.77 19.53 39.06 52.08 78.13 -- 78.13 -- -- -- % Error 103.45 0.16 0.16 1.73 1.73 1.73 -9.58 1.73 -- -32.18 -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 38.4 57.6 76.8 96.0 115.2 250.0 300.0 625.0
-- -- 255 64 32 15 10 7 6 4 2 1 0
-- 255 129 32 15 7 4 3 2 --
255 207 103 25 12 6 3 2 -- 1 0 -- --
255 129 64 15 7 3 2 1 -- 1 -- -- --
FOSC = 8.000000 MHz BAUD RATE (K) Actual Rate (K) 0.49 1.20 2.40 9.62 17.86 41.67 62.50 -- 125.00 % Error 62.76 0.16 0.16 0.16 -6.99 8.51 8.51 -- 8.51 SPBRG value
(decimal)
FOSC = 7.159090 MHz Actual Rate (K) 0.44 1.20 2.38 9.32 18.64 37.29 55.93 -- 111.86 % Error 45.65 0.23 -0.83 -2.90 -2.90 -2.90 -2.90 -- -2.90 SPBRG value
(decimal)
FOSC = 5.068800 MHz Actual Rate (K) 0.31 1.20 2.40 9.90 19.80 39.60 -- 79.20 -- % Error 3.13 0.00 0.00 3.13 3.13 3.13 -- 3.13 -- SPBRG value
(decimal)
FOSC = 4.000000 MHz Actual Rate (K) 0.30 1.20 2.40 8.93 20.83 31.25 62.50 -- -- % Error 0.16 0.16 0.16 -6.99 8.51 -18.62 8.51 -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 38.4 57.6 -- 115.2
255 103 51 12 6 2 1 -- 0
255 92 46 11 5 2 1 -- 0
255 65 32 7 3 1 -- 0 --
207 51 25 6 2 1 0 -- --
FOSC = 3.579545 MHz
FOSC = 2.000000 MHz Actual Rate (K) 0.30 1.20 2.40 10.42 15.63 31.25 -- % Error 0.16 0.16 0.16 8.51 -18.62 -18.62 -- SPBRG value
(decimal)
FOSC = 1.000000 MHz Actual Rate (K) 0.30 1.20 2.23 7.81 15.63 -- -- % Error 0.16 0.16 -6.99 -18.62 -18.62 -- -- SPBRG value
(decimal)
FOSC = 0.032768 MHz Actual Rate (K) 0.26 -- -- -- -- -- -- % Error -14.67 -- -- -- -- -- -- SPBRG value
(decimal)
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 38.4 57.6
Actual Rate (K) 0.30 1.19 2.43 9.32 18.64 -- 55.93
% Error 0.23 -0.83 1.32 -2.90 -2.90 -- -2.90
SPBRG value
(decimal)
185 46 22 5 2 -- 0
103 25 12 2 1 0 --
51 12 6 1 0 -- --
1 -- -- -- -- -- --
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TABLE 18-4:
BAUD RATE (K) 2.4 9.6 19.2 38.4 57.6 76.8 96.0 115.2 250.0 300.0 500.0 625.0 1000.0 1250.0
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1, HIGH SPEED)
FOSC = 20.000 MHz Actual Rate (K) 4.88 9.62 19.23 37.88 56.82 78.13 96.15 113.64 250.00 312.50 416.67 625.00 -- 1250.00 % Error 103.45 0.16 0.16 -1.36 -1.36 1.73 0.16 -1.36 0.00 4.17 -16.67 0.00 -- 0.00 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- 9.77 19.23 38.46 58.14 75.76 96.15 113.64 250.00 312.50 500.00 625.00 833.33 1250.00 % Error -- 1.73 0.16 0.16 0.94 -1.36 0.16 -1.36 0.00 4.17 0.00 0.00 -16.67 0.00 SPBRG value
(decimal)
FOSC = 16.000 MHz Actual Rate (K) 3.91 9.62 19.23 38.46 58.82 76.92 100.00 111.11 250.00 333.33 500.00 -- 1000.00 -- % Error 62.76 0.16 0.16 0.16 2.12 0.16 4.17 -3.55 0.00 11.11 0.00 -- 0.00 -- SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 2.44 9.63 18.94 39.06 56.82 78.13 89.29 125.00 208.33 312.50 -- 625.00 -- -- % Error 1.73 0.16 -1.36 1.73 -1.36 1.73 -6.99 8.51 -16.67 4.17 -- 0.00 -- -- SPBRG value
(decimal)
-- 255 129 64 42 32 25 21 9 7 4 3 2 1
255 129 64 32 21 15 12 10 4 3 2 1 -- 0
255 103 51 25 16 12 9 8 3 2 1 -- 0 --
255 64 32 15 10 7 6 4 2 1 -- 0 -- --
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 38.4 57.6 76.8 96.0 115.2 250.0 300.0 500.0
FOSC = 8.000000 MHz Actual Rate (K) -- 1.95 2.40 9.62 19.23 38.46 55.56 71.43 100.00 125.00 250.00 -- 500.00 % Error -- 62.76 0.16 0.16 0.16 0.16 -3.55 -6.99 4.17 8.51 0.00 -- 0.00 SPBRG value
(decimal)
FOSC = 7.159090 MHz Actual Rate (K) -- 1.75 2.41 9.52 19.45 37.29 55.93 74.57 89.49 111.86 223.72 -- 447.44 % Error -- 45.65 0.23 -0.83 1.32 -2.90 -2.90 -2.90 -6.78 -2.90 -10.51 -- -10.51 SPBRG value
(decimal)
FOSC = 5.068800 MHz Actual Rate (K) -- 1.24 2.40 9.60 18.64 39.60 52.80 79.20 -- 105.60 -- 316.80 -- % Error -- 3.13 0.00 0.00 -2.94 3.13 -8.33 3.13 -- -8.33 -- 5.60 -- SPBRG value
(decimal)
FOSC = 4.000 MHz Actual Rate (K) 0.98 1.20 2.40 9.62 19.23 35.71 62.50 83.33 -- 125.00 250.00 -- -- % Error 225.52 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 -- 8.51 0.00 -- -- SPBRG value
(decimal)
-- 255 207 51 25 12 8 6 4 3 1 -- 0
-- 255 185 46 22 11 7 5 4 3 1 -- 0
-- 255 131 32 16 7 5 3 -- 2 -- 0 --
255 207 103 25 12 6 3 2 -- 1 0 -- --
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 38.4 57.6 76.8 115.2 250.0
FOSC = 3.579545 MHz Actual Rate (K) 0.87 1.20 2.41 9.73 18.64 37.29 55.93 74.57 111.86 223.72 % Error 191.30 0.23 0.23 1.32 -2.90 -2.90 -2.90 -2.90 -2.90 -10.51 SPBRG value
(decimal)
FOSC = 2.000000 MHz Actual Rate (K) 0.49 1.20 2.40 9.62 17.86 41.67 62.50 -- 125.00 -- % Error 62.76 0.16 0.16 0.16 -6.99 8.51 8.51 -- 8.51 -- SPBRG value
(decimal)
FOSC = 1.000000 MHz Actual Rate (K) 0.30 1.20 2.40 8.93 20.83 31.25 62.50 -- -- -- % Error 0.16 0.16 0.16 -6.99 8.51 -18.62 8.51 -- -- -- SPBRG value
(decimal)
FOSC = 0.032768 MHz Actual Rate (K) 0.29 1.02 2.05 -- -- -- -- -- -- -- % Error -2.48 -14.67 -14.67 -- -- -- -- -- -- -- SPBRG value
(decimal)
255 185 92 22 11 5 3 2 1 0
255 103 51 12 6 2 1 -- 0 --
207 51 25 6 2 1 0 -- -- --
6 1 0 -- -- -- -- -- -- --
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TABLE 18-5:
BAUD RATE (K) 9.6 19.2 38.4 57.6 76.8 96.0 250.0 300.0 500.0 625.0 1000.0 1250.0
BAUD RATES FOR SYNCHRONOUS MODE (SYNC = 1)
FOSC = 20.000 MHz Actual Rate (K) -- 19.53 38.46 57.47 76.92 96.15 250.00 294.12 500.00 625.00 1000.00 1250.00 % Error -- 1.73 0.16 -0.22 0.16 0.16 0.00 -1.96 0.00 0.00 0.00 0.00 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 39.06 57.47 76.92 96.15 250.00 303.03 500.00 625.00 1000.00 1250.00 % Error -- -- 1.73 -0.22 0.16 0.16 0.00 1.01 0.00 0.00 0.00 0.00 SPBRG value
(decimal)
FOSC = 16.000 MHz Actual Rate (K) 15.63 19.23 38.46 57.97 76.92 95.24 250.00 307.69 500.00 666.67 1000.00 1333.33 % Error 62.76 0.16 0.16 0.64 0.16 -0.79 0.00 2.56 0.00 6.67 0.00 6.67 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 9.77 19.23 38.46 58.14 75.76 96.15 250.00 312.50 500.00 625.00 833.33 1250.00 % Error 1.73 0.16 0.16 0.94 -1.36 0.16 0.00 4.17 0.00 0.00 -16.67 0.00 SPBRG value
(decimal)
-- -- 255 173 129 103 39 32 19 15 9 7
-- 255 129 86 64 51 19 16 9 7 4 3
255 207 103 68 51 41 15 12 7 5 3 2
255 129 64 42 32 25 9 7 4 3 2 1
BAUD RATE (K) 2.4 9.6 19.2 38.4 57.6 76.8 96.0 250.0 300.0 500.0 625.0 1000.0 1250.0
FOSC = 8.000000 MHz Actual Rate (K) 7.81 9.62 19.23 38.46 57.14 76.92 95.24 250.00 285.71 500.00 666.67 1000.00 -- % Error 225.52 0.16 0.16 0.16 -0.79 0.16 -0.79 0.00 -4.76 0.00 6.67 0.00 -- SPBRG value
(decimal)
FOSC = 7.159090 MHz Actual Rate (K) 6.99 9.62 19.24 38.08 57.73 77.82 94.20 255.68 298.30 447.44 596.59 894.89 1789.77 % Error 191.30 0.23 0.23 -0.83 0.23 1.32 -1.88 2.27 -0.57 -10.51 -4.55 -10.51 43.18 SPBRG value
(decimal)
FOSC = 5.068800 MHz Actual Rate (K) 4.95 9.60 19.20 38.40 57.60 74.54 97.48 253.44 316.80 422.40 633.60 -- 1267.20 % Error 106.25 0.00 0.00 0.00 0.00 -2.94 1.54 1.38 5.60 -15.52 1.38 -- 1.38 SPBRG value
(decimal)
FOSC = 4.000 MHz Actual Rate (K) 3.91 9.62 19.23 38.46 58.82 76.92 100.00 250.00 333.33 500.00 -- 1000.00 -- % Error 62.76 0.16 0.16 0.16 2.12 0.16 4.17 0.00 11.11 0.00 -- 0.00 -- SPBRG value
(decimal)
255 207 103 51 34 25 20 7 6 3 2 1 --
255 185 92 46 30 22 18 6 5 3 2 1 0
255 131 65 32 21 16 12 4 3 2 1 -- 0
255 103 51 25 16 12 9 3 2 1 -- 0 --
FOSC = 3.579545 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 38.4 57.6 76.8 96.0 250.0 500.0 Actual Rate (K) -- -- 3.50 9.62 19.04 38.91 55.93 74.57 99.43 223.72 447.44 % Error -- -- 45.65 0.23 -0.83 1.32 -2.90 -2.90 3.57 -10.51 -10.51 SPBRG value
(decimal)
FOSC = 2.000000 MHz Actual Rate (K) -- 1.95 2.40 9.62 19.23 38.46 55.56 71.43 100.00 250.00 500.00 % Error -- 62.76 0.16 0.16 0.16 0.16 -3.55 -6.99 4.17 0.00 0.00 SPBRG value
(decimal)
FOSC = 1.000000 MHz Actual Rate (K) 0.98 1.20 2.40 9.62 19,.23 35.71 62.50 83.33 -- 250.00 -- % Error 225.52 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 -- 0.00 -- SPBRG value
(decimal)
FOSC = 0.032768 MHz Actual Rate (K) 0.30 1.17 2.73 8.19 -- -- -- -- -- -- -- % Error 1.14 -2.48 13.78 -14.67 -- -- -- -- -- -- -- SPBRG value
(decimal)
-- -- 255 92 46 22 15 11 8 3 1
-- 255 207 51 25 12 8 6 4 1 0
255 207 103 25 12 6 3 2 -- 0 --
26 6 2 0 -- -- -- -- -- -- --
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18.3 USART Asynchronous Mode
18.3.1
In this mode, the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). Asynchronous mode functions in all power managed modes except Sleep mode when call clock sources are stopped. When in PRI_IDLE mode, no changes to the Baud Rate Generator values are required; however, other power managed mode clocks may operate at another frequency than the primary clock. Therefore, the Baud Rate generator values may need adjusting. Asynchronous mode is selected by clearing bit, SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 18-1. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. Flag bit TXIF is not cleared immediately upon loading the Transmit Buffer register, TXREG. TXIF becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit TXIF indicated the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit, therefore, the user must poll this bit in order to determine whether the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin
TXIE
Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN
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FIGURE 18-2:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1
ASYNCHRONOUS TRANSMISSION
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
1 TCY
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 18-3:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag)
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 18-6:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 6 Bit 5 Bit 4 Bit 3 RBIE Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR Value on all other Resets
Bit 7
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE PIR1 PIE1 IPR1 RCSTA TXREG TXSTA Legend: Note 1: PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
TMR0IF INT0IF
0000 000x 0000 000u
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 FERR BRGH OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
CREN ADDEN SYNC --
USART Transmit Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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18.3.2 USART ASYNCHRONOUS RECEIVER 18.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 18-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 18.2 "USART Baud Rate Generator (BRG)"). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 1. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with address detect enable: Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is required, set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 1.
FIGURE 18-4:
USART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK / 64 or / 16 OERR FERR
SPBRG
MSb Stop (8) 7
RSR Register *** 1 0
LSb Start
Baud Rate Generator RX9 Pin Buffer and Control RC7/RX/DT
Data Recovery RX9D RCREG Register FIFO
SPEN 8 Interrupt RCIF RCIE Data Bus
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To set up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 18.2 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set Transmit bit, TX9. Can be used as address/data bit. 5. 6. 7. 8. Enable the transmission by setting bit TXEN which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
2. 3. 4.
FIGURE 18-5:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note:
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun) bit to be set.
TABLE 18-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Legend: Note 1:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR 0000 000x Value on all other Resets 0000 000u 0000 0000 0000 0000 1111 1111 0000 -00x 0000 0000 0000 -010 0000 0000
Bit 7 GIE/GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
TMR0IF INT0IF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 OERR TRMT RX9D TX9D 0000 -00x 0000 0000 0000 -010 0000 0000
CREN ADDEN FERR SYNC -- BRGH
USART Receive Register Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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18.4 USART Synchronous Master Mode
(PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a readonly bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.2 "USART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit, CSRC (TXSTA<7>).
18.4.1
USART SYNCHRONOUS MASTER TRANSMISSION
2. 3. 4. 5. 6. 7. 8.
The USART transmitter block diagram is shown in Figure 18-1. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TRMT `1'
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word 1
Write Word 2
TXEN bit Note:
`1'
Sync Master mode, SPBRG = 0; continuous transmission of two 8-bit words.
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FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7 RC7/RX/DT pin RC6/TX/CK pin
Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 18-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA Legend: Note 1: Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 1111 1111 0000 -00x 0000 0000 SYNC -- BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 0000 1111 1111 0000 -00x 0000 0000 0000 -010 0000 0000
GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE CCP1IP TMR2IP TMR1IP FERR OERR RX9D
CREN ADDEN
USART Transmit Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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18.4.2 USART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either enable bit, SREN (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.2 "USART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 4. 5. 6.
2. 3.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG Note: `0'
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Legend: Note 1:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on all other Resets
Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN SYNC
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 FERR BRGH OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
USART Receive Register Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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18.5 USART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any power managed mode. Slave mode is entered by clearing bit, CSRC (TXSTA<7>).
18.5.1
USART SYNCHRONOUS SLAVE TRANSMIT
2. 3. 4. 5. 6. 7. 8.
The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP
(1)
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9
Bit 5
Bit 4
Bit 3 RBIE SSPIF SSPIE SSPIP
Bit 2 TMR0IF
Bit 1 INT0IF
Bit 0 RBIF
Value on POR, BOR 0000 000x
Value on all other Resets 0000 000u 0000 0000 0000 0000 1111 1111 0000 -00x 0000 0000 0000 -010 0000 0000
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 CCP1IP TMR2IP TMR1IP 1111 1111 FERR BRGH OERR TRMT RX9D TX9D 0000 -00x 0000 0000 0000 -010 0000 0000
SPEN CSRC
CREN ADDEN SYNC --
USART Transmit Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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18.5.2 USART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to entering Sleep or any Idle mode, then a word may be received while in this power managed mode. Once the word is received, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from the power managed mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on all other Resets
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN SYNC
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 FERR BRGH OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
USART Receive Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2)
The Analog-to-Digital (A/D) converter module has 10 inputs for the PIC18F2X20 devices and 13 for the PIC18F4X20 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and setting the GO/DONE bit immediately. When the GO/DONE bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register 19-3 and Section 19.3 "Selecting and Configuring Automatic Acquisition Time").
The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 19-2, configures the functions of the port pins. The ADCON2 register, shown in Register 19-3, configures the A/D clock source, programmed acquisition time and justification.
REGISTER 19-1:
ADCON0 REGISTER
U-0 -- bit 7 U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 7-6 bit 5-3
Unimplemented: Read as `0' CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) Note 1: These channels are not implemented on the PIC18F2X20 (28-pin) devices. 2: Performing a conversion on unimplemented channels returns full-scale results.
bit 1
GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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REGISTER 19-2: ADCON1 REGISTER
U-0 -- bit 7 bit 7-6 bit 5 Unimplemented: Read as `0' VCFG1: Voltage Reference Configuration bit, VREFL Source 1 = VREF- (AN2) 0 = AVSS VCFG0: Voltage Reference Configuration bit, VREFH Source 1 = VREF+ (AN3) 0 = AVDD PCFG3:PCFG0: A/D Port Configuration Control bits AN7(2) AN6(2) AN9 AN8 AN4 AN3 AN2 AN1 A A A A A A A A A A A A A A D D AN0 A A A A A A A A A A A A A A A D PCFG3: PCFG0 0000(1) 0001 0010 0011 0100 0101 0110 0111(1) 1000 1001 1010 1011 1100 1101 1110 1111 AN5(2) AN12 AN10 AN11 U-0 -- R/W-0 VCFG1 R/W-0 VCFG0 R/W-q(1) PCFG3 R/W-q(1) PCFG2 R/W-q(1) PCFG1 R/W-q(1) PCFG0 bit 0
bit 4
bit 3-0
A A A D D D D D D D D D D D D D
A A A A D D D D D D D D D D D D
A A A A A D D D D D D D D D D D
A A A A A A D D D D D D D D D D
A A A A A A A D D D D D D D D D
A A A A A A A A D D D D D D D D
A A A A A A A A A D D D D D D D
A A A A A A A A A A D D D D D D
A A A A A A A A A A A D D D D D
A A A A A A A A A A A A D D D D
A A A A A A A A A A A A A D D D
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBAD bit in Configuration Register 3H. When PBAD = 1, PCFG<3:0> = 0000; when PBAD = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only in PIC18F4X20 devices. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 19-3: ADCON2 REGISTER
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS1:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0
bit 6 bit 5-3
bit 2-0
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The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 19-1.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0 1100 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 10-bit Converter A/D (Input Voltage) 0011 0010 VCFG1:VCFG0 AVDD VREFH VREFL
X0 X1
AN12(2) AN11 AN10 AN9 AN8 AN7(1) AN6(1) AN5(1) AN4 AN3/VREF+ AN2/VREFAN1 AN0
0001 0000
Reference Voltage
1X 0X AVSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2X20 devices. 2: I/O pins have diode protection to VDD and VSS.
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The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 19.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts.
3. 4. 5.
6. 7.
FIGURE 19-2:
ANALOG INPUT MODEL
VDD VT = 0.6V Rs ANx RIC 1k Sampling Switch SS RSS
VAIN
CPIN 5 pF VT = 0.6 V
ILEAKAGE 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN VT ILEAKAGE RIC SS CHOLD RSS
= input capacitance = threshold voltage = leakage current at the pin due to various junctions = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) = sampling switch resistance
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
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19.1 A/D Acquisition Requirements 19.2 A/D VREF+ and VREF- References
For the A/D converter to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. The maximum recommended impedance of the VREF+ and VREF- external reference voltage sources is 75. Note: When using external references, the source impedance of the external voltage references must be less than 75 in order to achieve the specified ADC resolution. A higher reference source impedance will increase the ADC offset and gain errors. Resistive voltage dividers will not provide a low enough source impedance. To ensure the best possible ADC performance, external VREF inputs should be buffered with an op amp or other low-impedance circuit.
To calculate the minimum acquisition time, Equation 19-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 19-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD RS Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0
EQUATION 19-1:
TACQ = =
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF
EQUATION 19-2:
VHOLD or TC = =
MINIMUM A/D HOLDING CAPACITOR
(VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 19-1:
= = =
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF TACQ TAMP 5 s TCOFF (Temp - 25C)(0.05 s/C) (50C - 25C)(0.05 s/C) 1.25 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. TC - -(CHOLD)(RIC + RSS + RS) ln(1/2047) s -(120 pF) (1 k + 7 k + 2.5 k) ln(0.0004883) s 9.61 s TACQ = 5 s + 1.25 s + 9.61 s 12.86 s
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19.3 Selecting and Configuring Automatic Acquisition Time 19.4 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator
The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun.
For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 2 s, see parameter #130 for more information). Table 19-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 19-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency PIC18FXX20 1.25 MHz 2.50 MHz 5.00 MHz 10.0 MHz 20.0 MHz 40.0 MHz 1.00 MHz(1) PIC18LFXX20(4) 666 kHz 1.33 MHz 2.66 MHz 5.33 MHz 10.65 MHz 21.33 MHz 1.00 MHz(2)
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC Note 1: 2: 3: 4:
(3)
ADCS2:ADCS0 000 100 001 101 010 110 x11
The RC source has a typical TAD time of 4 s. The RC source has a typical TAD time of 6 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power devices only.
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19.5 Operation in Power Managed Modes 19.6 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 3: The PBADEN bit in the Configuration register configures PORTB pins to reset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 are reset.
The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power managed mode. If the A/D is expected to operate while the device is in a power managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the power managed mode clock that will be used. After the power managed mode is entered (either of the power managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power managed Idle mode during the conversion. If the power managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires the A/D RC clock to be selected. If bits ACQT2:ACQT0 are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion.
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19.7 A/D Conversions
Figure 19-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 19-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are set to `010' and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b9 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL are loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles 1 2 3 4 1 2 b9 Automatic Acquisition Time 3 b8 4 b7
TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0
Conversion starts (Holding capacitor is disconnected)
Set GO bit (Holding capacitor continues acquiring input)
Next Q4: ADRESH:ADRESL are loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input.
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19.8 Use of the CCP2 Trigger
An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate TACQ time, selected before the "special event trigger", sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter.
TABLE 19-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTB TRISB LATB PORTE TRISE(3) LATE(3) Legend: Note 1: 2: 3: 4: Bit 7 GIE/ GIEH
SUMMARY OF A/D REGISTERS
Bit 6 PEIE/ GIEL ADIF ADIE ADIP CMIF CMIE CMIP Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP EEIF EEIE EEIP Bit 3 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Value on POR, BOR 0000 0000 0000 0000 0000 0000 1111 1111 00-0 0000 00-0 0000 11-1 1111 xxxx xxxx xxxx xxxx CHS3 VCFG0 ACQT1 RA4 CHS1 PCFG3 ACQT0 RA3 CHS0 PCFG2 ADCS2 RA2 GO/DONE PCFG1 ADCS1 RA1 ADON PCFG0 ADCS0 RA0 --00 0000 --00 qqqq 0-00 0000 --0x 0000 --11 1111 xxxx xxxx 1111 1111 xxxx xxxx -- IBOV -- -- PSPMODE -- RE3(2) -- Read PORTE pins, Write PORTE Data Direction LATE(4) ---- xxxx 0000 -111 ---- -xxx Value on all other Resets 0000 0000 0000 0000 0000 0000 1111 1111 00-0 0000 00-0 0000 11-1 1111 uuuu uuuu uuuu uuuu --00 0000 --00 qqqq 0-00 0000 --0u 0000 --11 1111 uuuu uuuu 1111 1111 uuuu uuuu ---- uuuu 0000 -111 ---- -uuu
PSPIF PSPIE PSPIP OSCFIF OSCFIE OSCFIP
A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM RA7(4) -- -- -- RA6(4) CHS3 VCFG1 ACQT2 RA5
TRISA7(4) TRISA6(4) Read PORTB pins, Write LATB Latch PORTB Data Direction Register PORTB Output Data Latch -- IBF -- -- OBE --
PORTE Output Data Latch
x = unknown, u = unchanged, - = unimplemented, read as `0', q = value depends on condition. Shaded cells are not used for A/D conversion. RE3 port bit is available only as an input pin when MCLRE bit in configuration register is `0'. This register is not implemented on PIC18F2X20 devices. These bits are not implemented on PIC18F2X20 devices. These pins may be configured as port pins depending on the oscillator mode selected.
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20.0 COMPARATOR MODULE
20.1 Comparator Configuration
The comparator module contains two analog comparators. The inputs and outputs for the comparators are multiplexed with the RA0 through RA5 pins. The onchip voltage reference (Section 21.0 "Comparator Voltage Reference Module") can also be an input to the comparators. The CMCON register, shown as Register 20-1, controls the comparator module's input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 20-1. There are eight modes of operation for the comparators. The CM bits (CMCON<2:0>) are used to select these modes. Figure 20-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in the Electrical Specifications (see Section 26.0 "Electrical Characteristics"). Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
REGISTER 20-1:
CMCON REGISTER
R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-1 CM2 R/W-1 CM1 R/W-1 CM0 bit 0
bit 7
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RA3/AN3 C2 VIN- connects to RA2/AN2 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 CM2:CM0: Comparator Mode bits Figure 20-1 shows the Comparator modes and CM2:CM0 bit settings. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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FIGURE 20-1:
Comparators RESET CM<2:0> = 000 RA0/AN0
D
COMPARATOR I/O OPERATING MODES
Comparators Off (POR Default Value) CM<2:0> = 111 RA0/AN0 C1 Off (Read as `0')
D
VINVIN+
VINVIN+ C1 Off (Read as `0')
RA3/AN3/ D VREF+ RA1/AN1
D
RA3/AN3/ D VREF+ RA1/AN1
D
VINVIN+ C2 Off (Read as `0')
VINVIN+ C2 Off (Read as `0')
RA2/AN2/ D VREF-/CVREF
RA2/AN2/ D VREF-/CVREF
Two Independent Comparators CM<2:0> = 010 RA0/AN0
A
Two Independent Comparators with Outputs CM<2:0> = 011 RA0/AN0
A A
VINVIN+ C1 C1OUT
VINVIN+ C1 C1OUT
RA3/AN3/ A VREF+ RA1/AN1
A
RA3/AN3/ VREF+
RA4/T0CKI/C1OUT(1) VINVIN+ C2 C2OUT RA1/AN1
A
VINVIN+ C2 C2OUT
RA2/AN2/ A VREF-/CVREF
RA2/AN2/ A VREF-/CVREF
RA5/AN4/SS/LVDIN/C2OUT(1) Two Common Reference Comparators CM<2:0> = 100 RA0/AN0 RA3/AN3/ VREF+ RA1/AN1
A A
Two Common Reference Comparators with Outputs CM<2:0> = 101 RA0/AN0
A A
VINVIN+ C1 C1OUT
VINVIN+ C1 C1OUT
RA3/AN3/ VREF+ RA4/T0CKI/C1OUT(1)
A
VINVIN+ C2 C2OUT RA1/AN1 RA2/AN2/ VREF-/CVREF
A D
RA2/AN2/ D VREF-/CVREF
VINVIN+ C2 C2OUT
RA5/AN4/SS/LVDIN/C2OUT(1) One Independent Comparator with Output CM<2:0> = 001 RA0/AN0 VREF+ RA4/T0CKI/C1OUT(1) RA1/AN1
D A
Four Inputs Multiplexed to Two Comparators CM<2:0> = 110 RA0/AN0
A A CIS = 0 CIS = 1
VINVIN+ C1 C1OUT
VINVIN+ VINVIN+ C2 C2OUT C1 C1OUT
RA3/AN3/ A
RA3/AN3/ VREF+ RA1/AN1
A A CIS = 0 CIS = 1 CVROE = 0
VINVIN+ C2 Off (Read as `0')
RA2/AN2/ VREF-/CVREF
RA2/AN2/ D VREF-/CVREF
CVREF
CVROE = 1
From VREF Module
A = Analog Input, port reads zeros always, overrides TRISA bit(2). D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch; CVROE (CVRCON<6>) is the Voltage Reference Output Switch. Note 1: 2: RA4 must be configured as an output pin in TRISA<4> when used to output C1OUT. RA5 ignores TRISA<5> when used as an output for C2OUT. Mode 110 is exception. Comparator input pins obey TRISA bits.
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20.2 Comparator Operation
20.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 20-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 21.0 "Comparator Voltage Reference Module" contains a detailed description of the comparator voltage reference module that provides this signal. The internal reference signal is used when comparators are in mode, CM2:CM0 = 110 (Figure 20-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. Depending on the setting of the CVROE bit (CVRCON<6>), the voltage reference may also be available on pin RA2.
20.3
Comparator Reference
An external or internal reference signal may be used depending on the comparator operating mode. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 20-2).
20.4
Comparator Response Time
FIGURE 20-2:
SINGLE COMPARATOR
VIN+ VIN-
+ -
Output
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Table 26-2 in Section 26.0 "Electrical Characteristics").
20.5
Comparator Outputs
VINVIN- VIN+ VIN+
Output Output
The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexers in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 20-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode.
20.3.1
EXTERNAL REFERENCE SIGNAL
The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the Port register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s).
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FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX + CxINV
To RA4 or RA5 Pin Bus Data Read CMCON Q EN D
Set CMIF bit
Q From other Comparator
D EN CL Read CMCON Reset
20.6
Comparator Interrupts
Note:
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the Comparator Interrupt Flag. The CMIF bit is cleared by firmware. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.
If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared.
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20.7 Comparator Operation in Power Managed Modes 20.9 Analog Input Connection Considerations
When a comparator is active and the device is placed in a power managed mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from a power managed mode when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in a power managed mode, turn off the comparators (CM<2:0> = 111) before entering the power managed modes. If the device wakes up from a power managed mode, the contents of the CMCON register are not affected.
A simplified circuit for an analog input is shown in Figure 20-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. Therefore, the analog input must be between VSS and VDD. If the input voltage exceeds this range by more than 0.6V, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources.
20.8
Effects of a Reset
A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Comparator Reset mode (CM<2:0> = 111). This ensures that all potential inputs are analog inputs. Device current is minimized when digital inputs are present at Reset time. The comparators will be powered down during the Reset interval.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD RS < 10k AIN VT = 0.6V RIC Comparator Input CPIN 5 pF VT = 0.6V ILEAKAGE 500 nA
VA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage
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TABLE 20-1:
Name CMCON INTCON PIR2 PIE2 IPR2 PORTA LATA TRISA
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 6 C1OUT PEIE/ GIEL CMIF CMIE CMIP RA6(1) -- -- Bit 5 C2INV CVRR Bit 4 C1INV -- Bit 3 CIS CVR3 RBIE BCLIF BCLIE BCLIP RA3 Bit 2 CM2 CVR2 TMR0IF LVDIF LVDIE LVDIP RA2 Bit 1 CM1 CVR1 INT0IF Bit 0 CM0 CVR0 RBIF Value on POR Value on all other Resets
Bit 7 C2OUT GIE/ GIEH -- -- -- RA7(1) -- --
0000 0111 0000 0111 000- 0000 000- 0000 0000 0000 0000 0000
CVRCON CVREN CVROE
TMR0IE INT0IE -- -- -- RA5 LATA -- -- -- RA4
TMR3IF CCP2IF -0-- 0000 -0-- 0000 TMR3IE CCP2IE -0-- 0000 -0-- 0000 TMR3IP CCP2IP -1-- 1111 -1-- 1111 RA1 RA0 xx0x 0000 xx0x 0000 xxxx xxxx xxxx xxxx 1111 1111 1111 1111
Data Output Register
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are unused by the comparator module. Note 1: These pins are enabled based on oscillator configuration (see Configuration Register 1H).
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21.0 COMPARATOR VOLTAGE REFERENCE MODULE
21.1 Configuring the Comparator Voltage Reference
The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 21-1. The block diagram is given in Figure 21-1. The comparator reference supply voltage comes from VDD and VSS.
The comparator voltage reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the comparator voltage reference are as follows:
EQUATION 21-1:
If CVRR = 1: VDD CVREF = (CVR<3:0>) * 24 If CVRR = 0: VDD CVREF = (CVR<3:0> + 8) * 32 The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 26-2 in Section 26.0 "Electrical Characteristics").
REGISTER 21-1:
CVRCON REGISTER
R/W-0 CVREN bit 7 R/W-0 CVROE R/W-0 CVRR U-0 -- R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF(1) pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin Note 1: CVROE overrides the TRISA<2> bit setting.
bit 6
bit 5
CVRR: Comparator VREF Range Selection bit 1 = 0.00 VDD to 0.75 VDD, with VDD/24 step size 0 = 0.25 VDD to 0.75 VDD, with VDD/32 step size Unimplemented: Read as `0' CVR3:CVR0: Comparator VREF Value Selection 0 VR3:VR0 15 bits When CVRR = 1: VDD CVREF = (CVR<3:0>) * 24 When CVRR = 0: VDD CVREF = 1/4 * (CVRSRC) + (CVR<3:0> + 8) * 32
bit 4 bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM
VDD 16 Stages CVREN 8R R R R R CVRR 8R
RA2/AN2/VREF-/CVREF
CVROE CVR3 (From CVRCON<3:0>) CVR0
CVREF
16-1 Analog Mux
21.2
Voltage Reference Accuracy/Error
21.4
Effects of a Reset
The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from VDD; therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the voltage reference can be found in Section 26.0 "Electrical Characteristics".
A device Reset disables the voltage reference by clearing the CVRCON register. This also disconnects the reference from the RA2 pin, selects the high-voltage range and selects the lowest voltage tap from the resistor divider.
21.5
Connection Considerations
21.3
Operation in Power Managed Modes
The contents of the CVRCON register are not affected by entry to or exit from power managed modes. To minimize current consumption in power managed modes, the voltage reference module should be disabled; however, this can cause an interrupt from the comparators so the comparator interrupt should also be disabled while the CVRCON register is being modified.
The voltage reference module operates independently of the comparator module. The output of the reference generator may be output using the RA2 pin if the CVROE bit is set. Enabling the voltage reference output onto the RA2 pin, with an input signal present, will increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, an external buffer must be used on the voltage reference output for external connections to VREF. Figure 21-2 shows an example buffering technique.
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FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
CVREF Module
R(1)
RA2
+ -
Voltage Reference Output Impedance
CVREF Output
Note 1: R is dependent upon the voltage reference configuration bits (CVRCON<3:0> and CVRCON<5>).
TABLE 21-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 6 Bit 5 CVRR C2INV RA5 Bit 4 -- C1INV RA4 Bit 3 CVR3 CIS RA3 Bit 2 CVR2 CM2 RA2 Bit 1 CVR1 CM1 RA1 Bit 0 CVR0 CM0 RA0 Value on POR Value on all other Resets
Bit 7
CVRCON CVREN CVROE CMCON TRISA C2OUT RA7(1) C1OUT RA6(1)
000- 0000 000- 0000 0000 0111 0000 0111 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used with the comparator voltage reference. Note 1: These pins are enabled based on oscillator configuration (see Configuration Register 1H).
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22.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks" before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect (LVD) module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be turned off by the software which minimizes the current consumption for the device. Figure 22-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference, TB - TA, is the total time for shutdown. The block diagram for the LVD module is shown in Figure 22-2. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 22-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
FIGURE 22-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
Voltage
VA VB
Legend: VA = LVD trip point VB = Minimum valid device operating voltage TB
Time
TA
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FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD LVDIN LVD Control Register
16 to 1 MUX
LVDIF
LVDEN
Internally Generated Reference Voltage 1.2V
The LVD module has an additional feature that allows the user to supply the sense voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input
pin, LVDIN (Figure 22-3). This gives users flexibility because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range.
FIGURE 22-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD VDD LVD Control Register LVDIN 16 to 1 MUX LVDEN LVD
Externally Generated Trip Point
VxEN BODEN
EN BGAP
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22.1 Control Register
The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
REGISTER 22-1:
LVDCON REGISTER
U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0
bit 7-6 bit 5
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.50V-4.78V 1101 = 4.20V-4.46V 1100 = 4.00V-4.26V 1011 = 3.80V-4.04V 1010 = 3.60V-3.84V 1001 = 3.50V-3.72V 1000 = 3.30V-3.52V 0111 = 3.00V-3.20V 0110 = 2.80V-2.98V 0101 = 2.70V-2.86V 0100 = 2.50V-2.66V 0011 = 2.40V-2.55V 0010 = 2.20V-2.34V 0001 = 2.00V-2.12V 0000 = Reserved Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested.
bit 4
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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22.2 Operation
Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register) which selects the desired LVD trip point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits).
2. 3. 4. 5.
6.
Figure 22-4 shows typical waveforms that the LVD module may be used to detect.
FIGURE 22-4:
CASE 1:
LOW-VOLTAGE DETECT WAVEFORMS
LVDIF may not be set VDD VLVD LVDIF
Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software
CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST
LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists
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22.2.1 REFERENCE VOLTAGE SET POINT
22.3
Operation During Sleep
The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36. The low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 22-4.
When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled.
22.4
Effects of a Reset
22.2.2
CURRENT CONSUMPTION
A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off.
When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B.
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23.0 SPECIAL FEATURES OF THE CPU
PIC18F2X20/4X20 devices include several features intended to maximize system reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2X20/4X20 devices have a Watchdog Timer which is either permanently enabled via the configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate configuration register bits.
23.1
Configuration Bits
The configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh) which can only be accessed using table reads and table writes. Programming the configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the configuration register sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 6.5 "Writing to Flash Program Memory".
TABLE 23-1:
File Name 300001h 300002h 300003h 300005h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFFh Legend: Note 1:
CONFIGURATION BITS AND DEVICE IDS
Bit 7 IESO -- -- MCLRE DEBUG -- CPD -- WRTD -- -- DEV2 DEV10 Bit 6 FSCM -- -- -- -- -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 -- -- -- -- -- -- -- -- WRTC -- -- DEV0 DEV8 Bit 4 -- -- -- -- -- -- -- -- -- -- REV4 DEV7 Bit 3 FOSC3 BORV1 -- -- CP3 -- WRT3 -- EBTR3 -- REV3 DEV6 Bit 2 FOSC2 BORV0 -- LVP CP2 -- WRT2 -- EBTR2 -- REV2 DEV5 Bit 1 FOSC1 BOR PBAD -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 Bit 0 FOSC0 PWRT WDT CCP2MX STVR CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 Default/ Unprogrammed Value 11-- 1111 ---- 1111 ---1 1111 1--- --11 1--- -1-1 ---- 1111 11-- ------- 1111 111- ------- 1111 -1-- ---xxxx xxxx(1) 0000 0101
CONFIG1H CONFIG2L CONFIG2H CONFIG3H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID2(1)
WDTPS3 WDTPS2 WDTPS1 WDTPS0
3FFFFEh DEVID1(1)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
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REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-1 IESO bit 7 bit 7 IESO: Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled FSCM: Fail-Safe Clock Monitor enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6 and port function on RA7 1000 = Internal oscillator block, port function on RA6 and port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R/P-1 FSCM U-0 -- U-0 -- R/P-1 FOSC3 R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0
bit 6
bit 5-4 bit 3-0
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REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- bit 7 bit 7-4 bit 3-2 Unimplemented: Read as `0' BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOR: Brown-out Reset enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRT: Power-up Timer enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOR R/P-1 PWRT bit 0
bit 1
bit 0
REGISTER 23-3:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 -- bit 7 U-0 -- U-0 -- R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDT bit 0
bit 7-5 bit 4-1
bit 0
Unimplemented: Read as `0' WDPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDT: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed
U = Unimplemented bit, read as `0' u = Unchanged from programmed state
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REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 MCLRE bit 7 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled Unimplemented: Read as `0' PBAD: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 PBAD R/P-1 CCP2MX bit 0
bit 6-2 bit 1
bit 0
REGISTER 23-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 DEBUG bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 LVP U-0 -- R/P-1 STVR bit 0
bit 7
DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug Unimplemented: Read as `0' LVP: Low-Voltage ICSP Enable bit 1 = Low-voltage ICSP enabled 0 = Low-voltage ICSP disabled Unimplemented: Read as `0' STVR: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 6-3 bit 2
bit 1 bit 0
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REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' CP3: Code Protection bit(1) 1 = Block 3 (001800-001FFFh) not code-protected 0 = Block 3 (001800-001FFFh) code-protected CP2: Code Protection bit(1) 1 = Block 2 (001000-0017FFh) not code-protected 0 = Block 2 (001000-0017FFh) code-protected CP1: Code Protection bit 1 = Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected CP0: Code Protection bit 1 = Block 0 (000200-0007FFh) not code-protected 0 = Block 0 (000200-0007FFh) code-protected Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/C-1 CP3(1) R/C-1 CP2(1) R/C-1 CP1 R/C-1 CP0 bit 0
bit 2
bit 1
bit 0
REGISTER 23-7:
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1 CPD bit 7 R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected CPB: Boot Block Code Protection bit 1 = Boot block (000000-0001FFh) not code-protected 0 = Boot block (000000-0001FFh) code-protected Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 6
bit 5-0
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REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' WRT3: Write Protection bit(1) 1 = Block 3 (001800-001FFFh) not write-protected 0 = Block 3 (001800-001FFFh) write-protected WRT2: Write Protection bit(1) 1 = Block 2 (001000-0017FFh) not write-protected 0 = Block 2 (001000-0017FFh) write-protected WRT1: Write Protection bit 1 = Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected WRT0: Write Protection bit 1 = Block 0 (000200-0007FFh) not write-protected 0 = Block 0 (000200-0007FFh) write-protected Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 WRT3(1) R/P-1 WRT2(1) R/P-1 WRT1 R/P-1 WRT0 bit 0
bit 2
bit 1
bit 0
REGISTER 23-9:
CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/P-1 WRTD bit 7 R/P-1 WRTB R-1 WRTC U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0001FFh) not write-protected 0 = Boot block (000000-0001FFh) write-protected WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note: This bit is read-only in normal execution mode; it can be written only in Program mode.
bit 6
bit 5
bit 4-0
Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
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REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' EBTR3: Table Read Protection bit(1) 1 = Block 3 (001800-001FFFh) not protected from table reads executed in other blocks 0 = Block 3 (001800-001FFFh) protected from table reads executed in other blocks EBTR2: Table Read Protection bit(1) 1 = Block 2 (001000-0017FFh) not protected from table reads executed in other blocks 0 = Block 2 (001000-0017FFh) protected from table reads executed in other blocks EBTR1: Table Read Protection bit 1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks EBTR0: Table Read Protection bit 1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 EBTR3(1) R/P-1 EBTR2(1) R/P-1 EBTR1 R/P-1 EBTR0 bit 0
bit 2
bit 1
bit 0
REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0001FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0001FFh) protected from table reads executed in other blocks Unimplemented: Read as `0' Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R/P-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5-0
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PIC18F2220/2320/4220/4320
REGISTER 23-12: DEVICE ID REGISTER 1 FOR PIC18F2220/2320/4220/4320 DEVICES
R DEV2 bit 7 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F4220 001 = PIC18F4320 100 = PIC18F2220 101 = PIC18F2320 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0
bit 4-0
REGISTER 23-13: DEVICE ID REGISTER 2 FOR PIC18F2220/2320/4220/4320 DEVICES
R DEV10 bit 7 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 0101 = PIC18F2220/2320/4220/4320 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0
Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
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23.2 Watchdog Timer (WDT)
For PIC18F2X20/4X20 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4> clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared.
23.2.1
CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit, but only if the configuration bit has disabled the WDT.
FIGURE 23-1:
WDT BLOCK DIAGRAM
Enable WDT INTRC Control
SWDTEN WDTEN INTRC Source Change on IRCF bits CLRWDT All Device Resets WDTPS<3:0> Sleep
WDT Counter /125 Wake-up from Sleep
Programmable Postscaler 1:1 to 1:32,768 4
Reset
WDT Reset
WDT
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REGISTER 23-14: WDTCON REGISTER
U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as `0' SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled. Legend: R = Readable bit U = Unimplemented bit, read as `0' W = Writable bit - n = Value at POR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN bit 0
TABLE 23-2:
Name CONFIG2H RCON WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 -- IPEN -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 WDTPS3 RI -- Bit 3 WDTPS2 TO -- Bit 2 WDTPS2 PD -- Bit 1 WDTPS0 POR -- Bit 0 WDTEN BOR SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
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23.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). Two-Speed Start-up is available only if the primary oscillator mode is LP, XT, HS or HSPLL (Crystal-based modes). Other sources do not require a OST start-up delay; for these, Two-Speed Start-up is disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a POR Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. In all other power managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
23.3.1
SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power managed modes, including serial SLEEP instructions (refer to Section 3.1.3 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode.
FIGURE 23-2:
INTOSC Multiplexer OSC1
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST(1) PLL Clock Output
TPLL(1) 1 2 3456 Clock Transition 7 8
CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note PC + 2 OSTS bit Set PC + 4 PC + 6
1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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23.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 23-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source but cleared on the rising edge of the sample clock. Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power managed mode (see Section 23.3.1 "Special Considerations for Using Two-Speed Start-up" and Section 3.1.3 "Multiple Sleep Commands" for more details). This can be done to attempt a partial recovery or execute a controlled shutdown. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. Adjustments to the internal oscillator block using the OSCTUNE register also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible.
FIGURE 23-3:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Peripheral Clock
S
Q
23.4.1
FSCM AND THE WATCHDOG TIMER
INTRC Source (32 s)
/ 64 488 Hz (2.048 ms)
C
Q
Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out.
Clock Failure Detected
Clock failure is tested on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 23-4). This causes the following: * The FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>) * The system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition) * The WDT is reset
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23.4.2 EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device Reset or by entering a power managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a Two-speed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power managed mode is entered. Entering a power managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the fail-safe condition. When the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock.
FIGURE 23-4:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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23.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES 23.4.4 POR OR WAKE FROM SLEEP
As previously mentioned, entering a power managed mode clears the fail-safe condition. By entering a power managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-safe monitoring of the power managed clock source resumes in the power managed mode. If an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. Instead, the device will continue to operate as before but clocked by the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the fail-safe condition is cleared. The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
As noted in Section 23.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary system clock to become stable. When the new powered managed mode is selected, the primary clock is disabled.
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23.5 Program Verification and Code Protection
Each of the five blocks has three code protection bits associated with them. They are: * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) Figure 23-5 shows the program memory organization for 4 and 8-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 23-3.
The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro(R) devices. The user program memory is divided into five blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into four blocks on binary boundaries.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2X20/4X20
MEMORY SIZE/DEVICE Block Code Protection Controlled By:
4 Kbytes (PIC18F2220/4220) Boot Block
8 Kbytes (PIC18F2320/4320) Boot Block
Address Range 000000h 0001FFh 000200h
CPB, WRTB, EBTRB
Block 0
Block 0 0007FFh 000800h
CP0, WRT0, EBTR0
Block 1
Block 1 000FFFh 001000h Block 2 0017FFh 001800h Block 3 001FFFh 002000h
CP1, WRT1, EBTR1
Unimplemented Read `0's Unimplemented Read `0's
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Unimplemented Read `0's
Unimplemented Read `0's
(Unimplemented Memory Space)
1FFFFFh
TABLE 23-3:
File Name 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh Legend:
SUMMARY OF CODE PROTECTION REGISTERS
Bit 7 -- CPD -- WRTD -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 CP3 -- WRT3 -- EBTR3 -- Bit 2 CP2 -- WRT2 -- EBTR2 -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 --
CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H
Shaded cells are unimplemented.
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23.5.1 PROGRAM MEMORY CODE PROTECTION
The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 23-6 through 23-8 illustrate table write and table read protection.
Note:
Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer.
FIGURE 23-6:
TABLE WRITE (WRTn) DISALLOWED
Program Memory 000000h 0001FFh 000200h WRTB, EBTRB = 11 Configuration Bit Settings
Register Values
TBLPTR = 0002FFh WRT0, EBTR0 = 01 PC = 0007FEh TBLWT * 0007FFh 000800h WRT1, EBTR1 = 11 000FFFh 001000h PC = 0017FEh TBLWT * 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table writes disabled to Blockn whenever WRTn = 0. WRT2, EBTR2 = 11
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FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Program Memory 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 0002FFh WRT0, EBTR0 = 10 0007FFh 000800h PC = 000FFEh TBLRD * 000FFFh 001000h WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'. WRT1, EBTR1 = 11 Configuration Bit Settings Register Values
FIGURE 23-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Program Memory 000000h WRTB, EBTRB = 11 0001FFh 000200h Configuration Bit Settings
Register Values
TBLPTR = 0002FFh PC = 0007FEh TBLRD * 0007FFh 000800h
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11 000FFFh 001000h WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.
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23.5.2 DATA EEPROM CODE PROTECTION
The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies.
23.9
Low-Voltage ICSP Programming
23.5.3
CONFIGURATION REGISTER PROTECTION
The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer.
The LVP bit in Configuration Register 4L (CONFIG4L<2>) enables Low-Voltage ICSP Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP pin, but the RB5/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. While programming using LVP, VDD is applied to the MCLR/VPP pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Low-Voltage Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 3: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. If Low-Voltage ICSP Programming mode will not be used, the LVP bit can be cleared and RB5/PGM becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/ VPP pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V.
23.6
ID Locations
Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected.
23.7
In-Circuit Serial Programming
PIC18F2X20/4X20 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed (see Table 23-5).
23.8
In-Circuit Debugger
When the DEBUG bit in configuration register, CONFIG4L, is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 23-4 shows which resources are required by the background debugger.
TABLE 23-5:
Signal Pin RB7 RB6 PGD PGC MCLR VDD VSS PGM
ICSP/ICD CONNECTIONS
Notes
TABLE 23-4:
I/O pins: Stack:
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 10 bytes
MCLR VDD VSS RB5
Program Memory: Data Memory:
May require isolation from application circuits
Pull RB5 low if LVP is enabled
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24.0 INSTRUCTION SET SUMMARY
The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word except for three double word instructions. These three instructions were made double word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 24-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 24-2, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 24.2 "Instruction Set" provides a description of each instruction. The PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations
The PIC18 instruction set summary in Table 24-2 lists byte-oriented, bit-oriented, literal and control operations. Table 24-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
24.1 READ-MODIFY-WRITE OPERATIONS
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a "BCF PORTB,1" instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch.
The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--')
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TABLE 24-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. Destination select bit: d = 0: store result in WREG d = 1: store result in file register f Destination either the WREG register or the specified register file location. 8-bit register file address (0x00 to 0xFF). 12-bit register file address (0x000 to 0xFFF). This is the source address. 12-bit register file address (0x000 to 0xFFF). This is the destination address. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No Change to register (such as TBLPTR with table reads and writes). Post-Increment register (such as TBLPTR with table reads and writes). Post-Decrement register (such as TBLPTR with table reads and writes). Pre-Increment register (such as TBLPTR with table reads and writes). The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) Unused or Unchanged. Working register (accumulator). Don't care (`0' or `1') . The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 21-bit Table Pointer (points to a Program Memory location). 8-bit Table Latch. Top-of-Stack. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Global Interrupt Enable bit. Watchdog Timer. Time-out bit. Power-down bit. ALU status bits Carry, Digit Carry, Zero, Overflow, Negative. Optional. Contents. Assigned to. Register bit field. In the set of. User defined term (font is courier).
bbb BSR d
dest f fs fd k label mm * *+ *+* n PRODH PRODL s
u WREG x
TBLPTR TABLAT TOS PC PCL PCH PCLATH PCLATU GIE WDT TO PD C, DC, Z, OV, N [ ( <> italics ] )
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FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 9 87 OPCODE d a 0 f (FILE #) ADDWF MYREG, W, B Example Instruction
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 f (Destination FILE #) 0 f (Source FILE #) 0 MOVFF MYREG1, MYREG2
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B
OPCODE b (BIT #) a
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 0x7F
n = 20-bit immediate value 15 OPCODE 15 12 11 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 11 10 n<10:0> (literal) 87 n<7:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 87 S n<7:0> (literal) 0 0 CALL MYFUNC
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TABLE 24-2:
Mnemonic, Operands
PIC18FXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF BCF BSF BTFSC BTFSS BTG f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, b, a f, b, a f, b, a f, b, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
None None C, DC, Z, OV, N 1, 2 C, Z, N Z, N 1, 2 C, Z, N Z, N None C, DC, Z, OV, N 1, 2
0101 11da 0101 10da
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N 1, 2 ffff None ffff None ffff Z, N ffff ffff ffff ffff ffff None None None None None 4 1, 2
1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba
BIT-ORIENTED FILE REGISTER OPERATIONS 1, 2 1, 2 3, 4 3, 4 1, 2
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 24-2:
Mnemonic, Operands CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation (Note 4) Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C, DC None
PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
0000 1100 0000 0000 0000 0000
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 24-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N
PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 (5) Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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24.2
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Set
ADD literal to W [ label ] ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z
0000 1111 kkkk kkkk
ADDWF k Syntax: Operands:
ADD W to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z
0010 01da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q2
Read literal `k' ADDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x15
Q4
Write to W
Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR is used. 1 1 Q2
Read register `f' ADDWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W W = =
Before Instruction
0x10 0x25
Q3
Process Data REG, W
Q4
Write to destination
After Instruction Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0xD9 0xC2
After Instruction
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ADDWFC Syntax: Operands: ADD W and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N, OV, C, DC, Z
0010 00da ffff ffff
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. k W N, Z
0000 1011 kkkk kkkk
f [,d [,a]]
k
Operation: Status Affected: Encoding: Description:
Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. 1 1
The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' ANDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x5F
Q4
Write to W
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q2
Read register `f' ADDWFC 1 0x02 0x4D 0 0x02 0x50
Q3
Process Data REG, W
Q4
Write to destination
Before Instruction
W W = = 0xA3 0x03
After Instruction
Example:
Carry bit = REG = W =
Before Instruction
After Instruction
Carry bit = REG = W =
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ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z
0001 01da ffff ffff
BC f [,d [,a]] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Carry [ label ] BC n -128 n 127 if carry bit is '1' (PC) + 2 + 2n PC None
1110 0010 nnnn nnnn
Operation: Status Affected: Encoding: Description:
The contents of W are AND'ed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden (default). 1 1 Q2
Read register `f' ANDWF
If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q3
Process Data REG, W
Q4
Write to destination
Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0x02 0xC2
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BC JUMP
Q4
No operation
After Instruction
Example:
PC
Before Instruction
address (HERE) 1; address (JUMP) 0; address (HERE+2)
After Instruction
If Carry PC If Carry PC
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BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None
1001 bbba ffff ffff
BN f,b[,a] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Negative [ label ] BN n -128 n 127 if negative bit is '1' (PC) + 2 + 2n PC None
1110 0110 nnnn nnnn
Operation: Status Affected: Encoding: Description:
Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' BCF
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data FLAG_REG, 7 No operation
Q4
Write register `f'
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BN Jump
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE+2)
After Instruction
If Negative PC If Negative PC
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BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if carry bit is '0' (PC) + 2 + 2n PC None
1110 0011 nnnn nnnn
BNN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Negative [ label ] BNN -128 n 127 if negative bit is '0' (PC) + 2 + 2n PC None
1110 0111 nnnn nnnn
n
n
If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNC Jump
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNN Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
After Instruction
If Carry PC If Carry PC
After Instruction
If Negative PC If Negative PC
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BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if overflow bit is '0' (PC) + 2 + 2n PC None
1110 0101 nnnn nnnn
BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Zero [ label ] BNZ -128 n 127 if zero bit is '0' (PC) + 2 + 2n PC None
1110 0001 nnnn nnnn
n
n
If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE+2)
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BNZ Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction After Instruction
If Overflow PC If Overflow PC
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
After Instruction
If Zero PC If Zero PC
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BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None
1101 0nnn nnnn nnnn
BSF Syntax: Operands:
Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None
1000 bbba ffff ffff
f,b[,a]
Operation: Status Affected: Encoding: Description:
Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal `n' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Bit `b' in register `f' is set. If `a' is `0', Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register `f' BSF = =
Words: Cycles: Q3
Process Data No operation
Q4
Write to PC No operation
Q Cycle Activity: Q1
Decode
Q3
Process Data FLAG_REG, 7 0x0A 0x8A
Q4
Write register `f'
Example: Example:
PC HERE = = BRA Jump
Before Instruction
FLAG_REG
Before Instruction
address (HERE) address (Jump)
After Instruction
FLAG_REG
After Instruction
PC
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BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None
1011 bbba ffff ffff
BTFSS Syntax: Operands:
Bit Test File, Skip if Set [ label ] BTFSS f,b[,a] 0 f 255 0b<7 a [0,1] skip if (f) = 1 None
1010 bbba ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3
Process Data
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q Cycle Activity: Q1
Decode
Q2
Read register `f'
Q4
No operation
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSC : :
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSS : :
Q4
No operation No operation
Example:
FLAG, 1
Example:
FLAG, 1
Before Instruction
PC address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction
PC address (HERE) 0; address (FALSE) 1; address (TRUE)
After Instruction
If FLAG<1> PC If FLAG<1> PC
After Instruction
If FLAG<1> PC If FLAG<1> PC
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BTG Syntax: Operands: Bit Toggle f [ label ] BTG f,b[,a] 0 f 255 0b<7 a [0,1] (f) f None
0111 bbba ffff ffff
BOV Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Overflow [ label ] BOV -128 n 127 if overflow bit is '1' (PC) + 2 + 2n PC None
1110 0100 nnnn nnnn
n
Operation: Status Affected: Encoding: Description:
Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' BTG = =
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data PORTC, 4 No operation
Q4
Write register `f'
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
PORTC PORTC
Before Instruction:
0111 0101 [0x75] 0110 0101 [0x65]
After Instruction:
If No Jump: Q1
Decode
Q2
Read literal `n' HERE = = = = =
Q3
Process Data BOV JUMP
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (JUMP) 0; address (HERE+2)
After Instruction
If Overflow PC If Overflow PC
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BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is '1' (PC) + 2 + 2n PC None
1110 0000 nnnn nnnn
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS None
1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal `n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If `s' = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2
Read literal `k'<7:0>, No operation HERE =
If No Jump: Q1
Decode
Words: Q2
Read literal `n' HERE = = = = =
Q3
Process Data BZ Jump
Q4
No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Push PC to stack No operation CALL
Q4
Read literal `k'<19:8>, Write to PC No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE+2)
After Instruction
If Zero PC If Zero PC
No operation
Example:
PC
THERE,FAST
Before Instruction
address (HERE) address (THERE) address (HERE + 4) W BSR STATUS
After Instruction
PC = TOS = WS = BSRS = STATUSS=
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CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [ label ] CLRF 0 f 255 a [0,1] 000h f 1Z Z
0110 101a ffff ffff
CLRWDT f [,a] Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD
0000 0000 0000 0100
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' CLRF = = 0x5A 0x00
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. 1 1 Q2
No operation CLRWDT = = = = = ? 0x00 0 1 1
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q3
Process Data FLAG_REG
Q4
Write register `f'
Decode
Example: Example: Before Instruction
FLAG_REG
Before Instruction
WDT Counter
After Instruction
WDT Counter WDT Postscaler
After Instruction
FLAG_REG
TO PD
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COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] ( f ) dest N, Z
0001 11da ffff ffff
CPFSEQ f [,d [,a]] Syntax: Operands: Operation:
Compare f with W, skip if f = W [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None
0110 001a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' COMF = = = 0x13 0x13 0xEC
Words: Cycles: Q Cycle Activity: Q1
Decode
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Q3
Process Data REG, W
Q4
Write to destination
Words: Cycles:
Example:
REG REG W
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NEQUAL EQUAL = = = = = = No operation No operation CPFSEQ REG : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Q4
No operation No operation
Example:
Before Instruction
PC Address W REG
After Instruction
If REG PC If REG PC
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CPFSGT Syntax: Operands: Operation: Compare f with W, skip if f > W [ label ] CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None
0110 010a ffff ffff
CPFSLT Syntax: Operands: Operation:
Compare f with W, skip if f < W [ label ] CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None
0110 000a ffff ffff
f [,a]
f [,a]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Compares the contents of data memory location 'f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected. If 'a' is `1', the BSR will not be overridden (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NLESS LESS = = < = = No operation No operation CPFSLT REG : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NGREATER GREATER = = > = = No operation No operation CPFSGT REG : :
Q4
No operation No operation
Example:
Example:
Before Instruction
PC W
Before Instruction
PC W Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
After Instruction
If REG PC If REG PC
After Instruction
If REG PC If REG PC
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DAW Syntax: Operands: Operation: Decimal Adjust W Register [ label ] DAW None If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: Description: C, DC
0000 0000 0000 0111
DECF Syntax: Operands:
Decrement f [ label ] DECF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z
0000 01da ffff ffff
Operation: Status Affected: Encoding: Description:
DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. The carry bit may be set by DAW regardless of its setting prior to the DAW execution. 1 1
Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' DECF = = = = 0x01 0 0x00 1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT,
Q4
Write to destination
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q2
Read register W DAW
Q3
Process Data
Q4
Write W
Before Instruction
CNT Z CNT Z
After Instruction
Example1:
W C DC W C DC = = = = = =
Before Instruction
0xA5 0 0 0x05 1 0
After Instruction
Example 2: Before Instruction
W C DC W C DC = = = = = = 0xCE 0 0 0x34 1 0
After Instruction
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DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None
0010 11da ffff ffff
DCFSNZ Syntax: Operands:
Decrement f, skip if not 0 [ label ] DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None
0100 11da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE CONTINUE No operation No operation DECFSZ GOTO
Q4
No operation No operation CNT LOOP
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = = = = No operation No operation DCFSNZ : : ? TEMP
Q4
No operation No operation
Example:
Example:
Before Instruction
PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2)
Before Instruction
TEMP
After Instruction
After Instruction
TEMP If TEMP PC If TEMP PC TEMP - 1, 0; Address (ZERO) 0; Address (NZERO)
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None
1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8
INCF Syntax: Operands:
Increment f [ label ] INCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z
0010 10da ffff ffff
Operation: Status Affected: Encoding: Description:
GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2
Words: Cycles: Q Cycle Activity: Q1
Decode
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' INCF = = = = = = = = 0xFF 0 ? ? 0x00 1 1 1
Words: Q2
Read literal `k'<7:0>, No operation
Q3
No operation No operation
Q4
Read literal `k'<19:8>, Write to PC No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT,
Q4
Write to destination
No operation
Example:
PC =
GOTO THERE Address (THERE)
Example:
CNT Z C DC CNT Z C DC
After Instruction
Before Instruction
After Instruction
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INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None
0011 11da ffff ffff
INFSNZ Syntax: Operands:
Increment f, skip if not 0 [ label ] INFSNZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None
0100 10da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO = = = = = No operation No operation INCFSZ : : CNT
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = No operation No operation INFSNZ REG
Q4
No operation No operation
Example:
Example:
Before Instruction
PC CNT If CNT PC If CNT PC Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction
PC REG If REG PC If REG PC Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
After Instruction
After Instruction
= = =
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IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k W N, Z
0000 1001 kkkk kkkk
IORWF Syntax: Operands:
Inclusive OR W with f [ label ] IORWF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z
0001 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The contents of W are OR'ed with the eight-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' IORLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x35
Q4
Write to W
Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' IORWF 0x13 0x91 0x13 0x93
Words: Example:
W W = =
Cycles: Q Cycle Activity: Q1
Decode
Before Instruction
0x9A 0xBF
Q3
Process Data RESULT, W
Q4
Write to destination
After Instruction
Example:
RESULT = W =
Before Instruction
After Instruction
RESULT = W =
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LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None
1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
MOVF Syntax: Operands:
Move f [ label ] MOVF f [,d [,a]] 0 f 255 d [0,1] a [0,1] f dest N, Z
0101 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The 12-bit literal `k' is loaded into the file select register pointed to by `f'. 2 2 Q2
Read literal `k' MSB
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write literal `k' MSB to FSRfH Write literal `k' to FSRfL
The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' MOVF = = = =
Decode
Read literal `k' LSB
Process Data
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
FSR2H FSR2L
LFSR 2, 0x3AB = = 0x03 0xAB
After Instruction
Q3
Process Data REG, W 0x22 0xFF 0x22 0x22
Q4
Write W
Example:
REG W
Before Instruction
After Instruction
REG W
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MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [ label ] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None
1100 1111 ffff ffff ffff ffff ffffs ffffd
MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to low nibble in BSR [ label ] k BSR None
0000 0001 kkkk kkkk
MOVLB k
0 k 255
The 8-bit literal `k' is loaded into the Bank Select Register (BSR). 1 1 Q2
Read literal `k'
The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see Page 87).
Q3
Process Data
Q4
Write literal `k' to BSR
Example:
MOVLB = =
5 0x02 0x05
Before Instruction
BSR register
After Instruction
BSR register
Words: Cycles: Q Cycle Activity: Q1
Decode
2 2 (3) Q2
Read register `f' (src) No operation No dummy read
Q3
Process Data No operation
Q4
No operation Write register `f' (dest)
Decode
Example:
REG1 REG2
MOVFF = = = =
REG1, REG2 0x33 0x11 0x33, 0x33
Before Instruction
After Instruction
REG1 REG2
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MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to W [ label ] kW None
0000 1110 kkkk kkkk
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move W to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (W) f None
0110 111a ffff ffff
MOVLW k
0 k 255
The eight-bit literal `k' is loaded into W. 1 1 Q2
Read literal `k' MOVLW
Q3
Process Data 0x5A
Q4
Write to W
Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' MOVWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W =
After Instruction
0x5A
Q3
Process Data REG
Q4
Write register `f'
Example:
W REG W REG = = = =
Before Instruction
0x4F 0xFF 0x4F 0x4F
After Instruction
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MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W [ label ] MULLW k 0 k 255 (W) x k PRODH:PRODL None
0000 1101 kkkk kkkk
MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply W with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None
0000 001a ffff ffff
An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1 Q2
Read literal `k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write registers PRODH: PRODL
An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a'= 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W PRODH PRODL
MULLW
0xC4
Before Instruction
= = = = = = 0xE2 ? ? 0xE2 0xAD 0x08
Q3
Process Data
Q4
Write registers PRODH: PRODL
After Instruction
W PRODH PRODL
Example:
W REG PRODH PRODL
MULWF
REG
Before Instruction
= = = = = = = = 0xC4 0xB5 ? ? 0xC4 0xB5 0x8A 0x94
After Instruction
W REG PRODH PRODL
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NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [ label ] NEGF f [,a] 0 f 255 a [0,1] (f)+1f N, OV, C, DC, Z
0110 110a ffff ffff
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
No Operation [ label ] None No operation None
0000 1111 0000 xxxx 0000 xxxx 0000 xxxx
NOP
Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register `f' NEGF = =
No operation. 1 1 Q2
No operation
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q3
Process Data REG, 1
Q4
Write register `f'
None.
Example:
REG REG
Before Instruction
0011 1010 [0x3A] 1100 0110 [0xC6]
After Instruction
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POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None
0000 0000 0000 0110
PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description:
Push Top of Return Stack [ label ] None (PC+2) TOS None
0000 0000 0000 0101
POP
PUSH
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2
No operation POP GOTO
The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, and then push it onto the return stack. 1 1 Q2
PUSH PC+2 onto return stack PUSH = = 0x00345A 0x000124
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
No operation
Q4
No operation
Q3
POP TOS value
Q4
No operation
Example: Example:
NEW = = 0x0031A2 0x014332 TOS PC
Before Instruction
Before Instruction
TOS Stack (1 level down)
After Instruction
PC TOS Stack (1 level down) = = = 0x000126 0x000126 0x00345A
After Instruction
TOS PC = = 0x014332 NEW
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RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None
1101 1nnn nnnn nnnn
RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All
0000 0000 1111 1111
RESET
Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal `n' Push PC to stack
This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2
Start reset RESET Reset Value Reset Value
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
Registers = Flags* =
After Instruction Q3
Process Data
Q4
Write to PC
No operation
No operation HERE
No operation RCALL Jump
No operation
Example:
PC = PC = TOS =
Before Instruction
Address (HERE) Address (Jump) Address (HERE+2)
After Instruction
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RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. GIE/GIEH, PEIE/GIEL.
0000 0000 0001 000s
RETLW Syntax: Operands: Operation:
Return Literal to W [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None
0000 1100 kkkk kkkk
RETFIE [s]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation
W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2
Read literal `k' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data No operation
Q4
pop PC from stack, Write to W No operation
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value
Q3
No operation
Q4
pop PC from stack Set GIEH or GIEL
No operation
No operation RETFIE 1
No operation
No operation
W = offset Begin table
Example: After Interrupt
End of table
PC W BSR STATUS GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
Before Instruction
W W = = 0x07 value of kn
After Instruction
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RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None
0000 0000 0001 001s
RLCF Syntax: Operands:
Rotate Left f through Carry [ label ] RLCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z
0011 01da ffff ffff
RETURN [s]
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation No operation
The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Words: Q3
Process Data No operation
1 1 Q2
Read register `f' RLCF = = = = =
Q4
pop PC from stack No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, W
Q4
Write to destination
Example: Example: After Interrupt
PC = TOS RETURN REG C REG W C
Before Instruction
1110 0110 0 1110 0110 1100 1100 1
After Instruction
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RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z
0100 01da ffff ffff
RRCF Syntax: Operands:
Rotate Right f through Carry [ label ] RRCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z
0011 00da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation:
Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default).
register f
The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Words: Q2
Read register `f' RLNCF = =
1 1 Q2
Read register `f' RRCF = = = = =
Q3
Process Data REG
Q4
Write to destination
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, W
Q4
Write to destination
Example:
REG REG
Before Instruction
1010 1011 0101 0111
Example:
REG C REG W C
After Instruction
Before Instruction
1110 0110 0 1110 0110 0111 0011 0
After Instruction
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RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z
0100 00da ffff ffff
SETF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Set f [ label ] SETF 0 f 255 a [0,1] FFh f None
0110 100a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default).
register f
The contents of the specified register are set to FFh. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SETF = =
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG 0x5A 0xFF
Q4
Write register `f'
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Q2
Read register `f' RRNCF = =
Example: Q3
Process Data REG, 1, 0
Before Instruction Q4
Write to destination REG
After Instruction
REG
Example 1:
REG REG
Before Instruction
1101 0111 1110 1011 RRNCF REG, W
After Instruction
Example 2:
W REG W REG = = = =
Before Instruction
? 1101 0111 1110 1011 1101 0111
After Instruction
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SLEEP Syntax: Operands: Operation: Enter SLEEP mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD
0000 0000 0000 0011
SUBFWB Syntax: Operands:
Subtract f from W with borrow [ label ] SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z
0101 01da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1 Words: Q2
No operation SLEEP ? ? 1 0
Words: Cycles: Q Cycle Activity: Q1
Decode
Subtract register `f' and carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `d' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Q3
Process Data
Q4
Go to Sleep
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Example:
TO = PD = TO = PD =
Before Instruction
Example 1:
REG W C REG W C Z N = = = = = = = =
SUBFWB REG 0x03 0x02 0x01 0xFF 0x02 0x00 0x00 0x01 SUBFWB = = = = = = = = 2 5 1 2 3 1 0 0
After Instruction
Before Instruction
If WDT causes wake-up, this bit is cleared.
After Instruction
; result is negative REG, 0, 0
Example 2:
REG W C REG W C Z N
Before Instruction
After Instruction
; result is positive REG, 1, 0
Example 3:
REG W C REG W C Z N = = = = = = = =
SUBFWB 1 2 0 0 2 1 1 0
Before Instruction
After Instruction
; result is zero
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SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z
0000 1000 kkkk kkkk
SUBWF Syntax: Operands:
Subtract W from f [ label ] SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z
0101 11da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k' SUBLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x02
Q4
Write to W
Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If = `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SUBWF = = = = = = = = 3 2 ? 1 2 1 0 0 SUBWF = = = = = = = = 2 2 ? 2 0 1 1 0 SUBWF = = = = = = = = 0x01 0x02 ? 0xFFh ;(2's complement) 0x02 0x00 ; result is negative 0x00 0x01
Example 1:
W C W C Z N = = = = = =
Words: Cycles: Q Cycle Activity: Q1
Decode
Before Instruction
1 ? 1 1 0 0 SUBLW
After Instruction
; result is positive
Q3
Process Data REG
Q4
Write to destination
Example 1:
0x02 REG W C REG W C Z N
Example 2:
W C W C Z N = = = = = =
Before Instruction
Before Instruction
2 ? 0 1 1 0 SUBLW
After Instruction
After Instruction
; result is zero
; result is positive
Example 3:
W C W C Z N = = = = = =
0x02
Example 2:
REG W C
REG, W
Before Instruction
3 ? FF 0 0 1 ; (2's complement) ; result is negative
Before Instruction
After Instruction
After Instruction
REG W C Z N
; result is zero
Example 3:
REG W C REG W C Z N
REG
Before Instruction
After Instruction
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SUBWFB Syntax: Operands: Subtract W from f with Borrow [ label ] SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z
0101 10da ffff ffff
Example 1:
REG W C REG W C Z N = = = = = = = =
SUBWFB 0x19 0x0D 0x01 0x0C 0x0D 0x01 0x00 0x00
REG, 1, 0
f [,d [,a]]
Before Instruction
(0001 1001) (0000 1101)
After Instruction
(0000 1011) (0000 1101) ; result is positive
Operation: Status Affected: Encoding: Description:
Subtract W and the carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f'
Example 2:
REG W C REG W C Z N = = = = = = = =
SUBWFB REG, 0, 0 0x1B 0x1A 0x00 0x1B 0x00 0x01 0x01 0x00 SUBWFB = = = = = = = = 0x03 0x0E 0x01 0xF5 0x0E 0x00 0x00 0x01
Before Instruction
(0001 1011) (0001 1010)
After Instruction
(0001 1011)
; result is zero REG, 1, 0
Words: Cycles: Q Cycle Activity: Q1
Decode
Example 3:
REG W C REG W C Z N
Before Instruction Q3
Process Data
Q4
Write to destination
(0000 0011) (0000 1101)
After Instruction
(1111 0100) ; [2's comp] (0000 1101) ; result is negative
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SWAPF Syntax: Operands: Swap f [ label ] SWAPF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None
0011 10da ffff ffff
Operation: Status Affected: Encoding: Description:
The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' SWAPF = = 0x53 0x35
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG
Q4
Write to destination
Example:
REG REG
Before Instruction After Instruction
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TBLRD Syntax: Operands: Operation: Table Read [ label ] None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT;
0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
TBLRD Example1:
Table Read (cont'd)
TBLRD *+ ; = = = = = TBLRD +* ; = = = = = = 0xAA 0x01A357 0x12 0x34 0x34 0x01A358 0x55 0x00A356 0x34 0x34 0x00A357
TBLRD ( *; *+; *-; +*)
Before Instruction
TABLAT TBLPTR MEMORY(0x00A356)
After Instruction
TABLAT TBLPTR
Example2:
Before Instruction
TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358)
Status Affected:None Encoding:
After Instruction
TABLAT TBLPTR
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q2
No operation No operation (Read Program Memory)
Words: Cycles:
Q Cycle Activity: Q1
Decode No operation
Q3
No operation
Q4
No operation
No No operation operation (Write TABLAT)
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TBLWT Syntax: Operands: Operation: Table Write [ label ] None if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Holding Register;
0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
TBLWT Table Write (Continued) Words: 1 Cycles: 2 Q Cycle Activity: Q1
Decode No operation
TBLWT ( *; *+; *-; +*)
Q2
No operation No operation (Read TABLAT)
Q3
No operation No operation
Q4
No operation No operation (Write to Holding Register )
Example1:
TBLWT
*+;
= = = = = = 0x55 0x00A356 0xFF 0x55 0x00A357 0x55
Status Affected: None Encoding:
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x00A356) TABLAT TBLPTR HOLDING REGISTER (0x00A356)
After Instructions (table write completion)
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment
Example 2:
TBLWT
+*;
= = = = = = = = 0x34 0x01389A 0xFF 0xFF 0x34 0x01389B 0xFF 0x34
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B)
After Instruction (table write completion)
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TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None
0110 011a ffff ffff
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W N, Z
0000 1010 kkkk kkkk
If `f' = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a twocycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register `f'
The contents of W are XOR'ed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2
Read literal `k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to W
Words: Cycles:
Example:
W W = =
XORLW 0xAF
0xB5 0x1A
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO No operation No operation TSTFSZ : : CNT
Q4
No operation No operation
Example:
Before Instruction
PC = Address (HERE)
After Instruction
If CNT PC If CNT PC = = = 0x00, Address (ZERO) 0x00, Address (NZERO)
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XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z
0001 10da ffff ffff
f [,d [,a]]
Operation: Status Affected: Encoding: Description:
Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register `f' XORWF = = = = 0xAF 0xB5 0x1A 0xB5
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG
Q4
Write to destination
Example:
REG W REG W
Before Instruction
After Instruction
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25.0 DEVELOPMENT SUPPORT
25.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) - PICDEM MSC - microID(R) - CAN - PowerSmart(R) - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - absolute listing file (mixed assembly and C) - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
25.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
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25.3 MPLAB C17 and MPLAB C18 C Compilers 25.6 MPLAB ASM30 Assembler, Linker and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
25.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
25.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
25.5
MPLAB C30 C Compiler
25.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many commandline options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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25.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 25.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
25.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode.
25.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
25.13 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
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25.14 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
25.17 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
25.18 PICDEM 4 8/14/18-Pin Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2x16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide.
25.15 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
25.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion.
25.16 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers.
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25.20 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
25.23 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
25.24 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and evaluation kits.
25.21 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
25.22 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the user's guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.
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26.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 26-1: PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18F2X20/4X20 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
40 MHz
Frequency
FIGURE 26-2:
PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V 5.5V 5.0V PIC18F2X20/4X20 4.2V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
25 MHz
Frequency
DS39599C-page 306
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-3: PIC18LF2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V
PIC18LF2X20/4X20
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
4.2V
4 MHz
40 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application.
2003 Microchip Technology Inc.
DS39599C-page 307
PIC18F2220/2320/4220/4320
26.1 DC Characteristics: Supply Voltage PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Symbol VDD D001 D002 D003 VDR VPOR Characteristic Supply Voltage PIC18LF2X20/4X20 PIC18F2X20/4X20 RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage
2.0 4.2 1.5 --
-- -- -- --
5.5 5.5 -- 0.7
V V V V
HS, XT, RC and LP Osc mode
See section on Power-on Reset for details
D004
SVDD
0.05
--
--
V/ms See section on Power-on Reset for details
VBOR D005
PIC18LF2X20/4X20 Industrial Low Voltage BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005 BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005E BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 Legend: Note 1: NA 2.50 3.88 4.18 NA 3.88 4.18 NA 3.71 4.00 -- 2.72 4.22 4.54 -- 4.22 4.54 -- 4.22 4.54 NA 2.94 4.56 4.90 NA 4.56 4.90 NA 4.73 5.08 V V V V V V V V V V Not in operating voltage range of device Not in operating voltage range of device Reserved
PIC18F2X20/4X20 Industrial
PIC18F2X20/4X20 Extended
Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
DS39599C-page 308
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device
Power-down Current (IPD)(1) PIC18LF2X20/4X20 0.1 0.1 0.2 PIC18LF2X20/4X20 0.1 0.1 0.3 All devices 0.1 0.1 0.4 Extended devices Supply Current (IDD)
(2,3)
0.5 0.5 1.7 0.5 0.5 1.7 2.0 2.0 6.5 50 25 25 25 40 40 40 80 80 80 80
A A A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V, (Sleep mode) VDD = 3.0V, (Sleep mode) VDD = 2.0V, (Sleep mode)
11.2 11 13 14
PIC18LF2X20/4X20
VDD = 2.0V
PIC18LF2X20/4X20
34 28 25
VDD = 3.0V
FOSC = 31 kHz (RC_RUN mode, internal oscillator source)
All devices
77 62 53
VDD = 5.0V
Extended devices Legend: Note 1:
50
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 309
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF2X20/4X20
100 110 120
220 220 220 330 330 330 550 550 550 650 600 600 600 900 900 900 1.8 1.8 1.8 1.8
A A A A A A A A A A A A A A A A mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, internal oscillator source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, internal oscillator source) VDD = 2.0V
PIC18LF2X20/4X20
180 180 170
All devices
340 330 310
Extended devices PIC18LF2X20/4X20
410 350 360 370
PIC18LF2X20/4X20
580 580 560
All devices
1.1 1.1 1.0
Extended devices Legend: Note 1:
1.2
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39599C-page 310
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF2X20/4X20
4.7 4.6 5.1
8 8 11 11 11 15 16 16 22 75 150 150 150 180 180 180 300 300 300 435
A A A A A A A A A A A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, internal oscillator source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, internal oscillator source) VDD = 2.0V
PIC18LF2X20/4X20
6.9 6.3 6.8
All devices
12 10 10
Extended devices PIC18LF2X20/4X20
25 49 52 56
PIC18LF2X20/4X20
73 77 77
All devices
130 130 130
Extended devices Legend: Note 1:
350
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 311
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF2X20/4X20
140 140 150
275 275 275 375 375 375 800 800 800 800 250 250 250 350 350 350 1.0 1.0 1.0 1.0
A A A A A A A A A A A A A A A A mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 1 MHZ (PRI_RUN, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, internal oscillator source) VDD = 2.0V
PIC18LF2X20/4X20
220 220 210
All devices
390 400 380
Extended devices PIC18LF2X20/4X20
410 150 150 160
PIC18LF2X20/4X20
340 300 280
All devices
0.72 0.63 0.57
Extended devices Legend: Note 1:
0.53
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39599C-page 312
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF2X20/4X20
440 450 460
600 600 600 1.0 1.0 1.0 2.0 2.0 2.0 2.0 9.0 10.0 12 12 12 15 15 15
A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 4.2V FOSC = 40 MHZ (PRI_RUN, EC oscillator) VDD = 4.2V VDD = 5.0V FOSC = 25 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 2.0V
PIC18LF2X20/4X20
0.80 0.78 0.77
All devices
1.6 1.5 1.5
Extended devices Extended devices
1.5 6.3 7.9
All devices
9.5 9.7 9.9
All devices
11.9 12.1 12.3
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 313
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) PIC18LF2X20/4X20
37 37 38
50 50 60 80 80 100 180 180 180 300 180 180 180 280 280 280 525 525 525 800 3.0 3.5
A A A A A A A A A A A A A A A A A A A A mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C VDD = 4.2V VDD = 5.0V FOSC = 25 MHZ (PRI_IDLE, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V
PIC18LF2X20/4X20
58 59 60
All devices
110 110 110
Extended devices PIC18LF2X20/4X20
125 140 140 140
PIC18LF2X20/4X20
220 230 230
All devices
410 420 430
Extended devices Extended devices
450 2.2 2.7
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39599C-page 314
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device Supply Current (IDD)(2,3) All devices
3.1 3.2 3.3
4.1 4.1 4.1 5.1 5.1 5.1 15 15 18 30 30 35 80 80 85 9 9 11 12 12 14 20 20 25
mA mA mA mA mA mA A A A A A A A A A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 2.0V VDD = 5.0V VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator)
All devices
4.4 4.6 4.6
PIC18LF2X20/4X20
9 10 13
PIC18LF2X20/4X20
22 21 20
All devices
50 50 45
PIC18LF2X20/4X20
5.1 5.8 7.9
PIC18LF2X20/4X20
7.9 8.9 10.5
All devices
13 16 18
Legend: Note 1:
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 315
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. Device
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) Watchdog Timer 1.5 2.2 2.7 2.3 2.7 3.1 3.0 3.3 3.9 Extended devices only D022A (IBOR) Extended devices only D022B (ILVD) Extended devices only Legend: Note 1: Low-Voltage Detect Brown-out Reset 4.0 17 47 48 14 18 21 24 3.8 3.8 4.0 4.6 4.6 4.8 10.0 10.0 10.0 13.0 35.0 45.0 50.0 25.0 35.0 45.0 50.0 A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C to +85C -40C to +85C -40C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +125C VDD = 3.0V VDD = 5.0V VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V VDD = 3.0V VDD = 2.0V
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
DS39599C-page 316
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ 2.1 1.8 2.1 2.2 2.6 2.9 3.0 3.2 3.4 D026 (IAD) A/D Converter 1.0 1.0 1.0 Extended devices only Legend: Note 1: 1.0 Max 2.2 2.2 2.2 3.8 3.8 3.8 6.0 6.0 7.0 2.0 2.0 2.0 8.0 Units A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C to +85C -40C to +85C -40C to +85C -40C to +125C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V A/D on, not converting VDD = 5.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 2.0V 32 kHz on Timer1(4) Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. D025 (IOSCB) Device Timer1 Oscillator
2:
3: 4:
Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O ports: D030 D030A D031 D032 D032A D033 VIH D040 D040A D041 D042 D042A D043 IIL D060 D061 D063 IPU D070 Note 1: 2: IPURB with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 and T1OSI OSC1 Input Leakage I/O ports MCLR, RA4 OSC1 Weak Pull-up Current PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Current(2,3) -- -- -- 0.2 1.0 1.0 A A A VSS VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 and T1OSI OSC1 Input High Voltage I/O ports: with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 0.8 VDD 1.6 0.8 VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V LP, XT, HS, HSPLL modes(1) EC mode(1) VDD < 4.5V 4.5V VDD 5.5V with TTL buffer VSS -- VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.2 VDD V V V V V V V LP, XT, HS, HSPLL modes(1) EC mode(1) VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param Symbol No. VIL
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.
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26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Output Low Voltage I/O ports -- -- OSC2/CLKO (RC mode) -- -- VOH D090 D090A D092 D092A D150 VOD Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin
--
DC CHARACTERISTICS Param Symbol No. VOL D080 D080A D083 D083A Output High Voltage(3) I/O ports
Min
Max
Units
Conditions
0.6 0.6 0.6 0.6
V V V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin
VDD - 0.7 VDD - 0.7
-- -- -- -- 8.5
V V V V V
OSC2/CLKO (RC mode)
VDD - 0.7 VDD - 0.7 --
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1 To meet the AC Timing Specifications In I2C mode
D101 D102 Note 1: 2:
CIO CB
All I/O pins and OSC2 (in RC mode) SCL, SDA
-- --
50 400
pF pF
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.
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TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Internal Program Memory Programming Specifications D110 D112 D113 VPP IPP IDDP Voltage on MCLR/VPP pin Current into MCLR/VPP pin Supply Current during Programming Data EEPROM Memory D120 D121 ED VDRW Byte Endurance VDD for Read/Write 100K 10K VMIN 1M 100K -- -- -- 5.5 E/W -40C to +85C E/W -40C to +125C V Using EECON to read/write VMIN = Minimum operating voltage 9.00 -- -- -- -- -- 13.25 300 1.0 V A mA (Note 2) Min Typ Max Units Conditions DC Characteristics Param No.
Sym
D122 D123 D124
TDEW
Erase/Write Cycle Time
-- 40 1M 100K 10K 1K VMIN 4.5 4.5 VMIN -- 1 -- 40
4 -- 10M 1M 100K 10K -- -- -- -- 4 -- 2 --
-- -- -- -- -- -- 5.5 5.5 5.5 5.5 -- -- -- --
ms Year Provided no other specifications are violated E/W -40C to +85C E/W -40C to +125C E/W -40C to +85C E/W -40C to +125C V V V V ms ms ms Year Provided no other specifications are violated VMIN = Minimum operating voltage Using ICSP port Using ICSP port VMIN = Minimum operating voltage VDD > 4.5V VDD > 4.5V
TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory Cell Endurance VDD for Read VDD for Block Erase VDD for Externally Timed Erase or Write VDD for Self-timed Write ICSP Block Erase Cycle Time ICSP Erase or Write Cycle Time (externally timed) Self-timed Write Cycle Time
D130 D131 D132
EP VPR VIE
D132A VIW D132B VPEW D133 TIE
D133A TIW D133A TIW D134
TRETD Characteristic Retention
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section 7.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 2: Required only if Low-Voltage Programming is disabled.
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TABLE 26-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C, unless otherwise stated. Param No. D300 D301 D302 300 300A 301 * Note 1: Sym VIOFF VICM CMRR TRESP TMC2OV Characteristics Input Offset Voltage Input Common Mode Voltage* Common Mode Rejection Ratio* Response Time(1)* Comparator Mode Change to Output Valid* Min -- 0 55 -- -- Typ 5.0 -- -- 150 -- Max 10 VDD - 1.5 -- 400 600 10 Units mV V dB ns ns s PIC18FXX20 PIC18LFXX20 Comments
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
TABLE 26-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C, unless otherwise stated. Param No. D310 D311 D312 310 * Note 1: Sym VRES VRAA VRUR TSET Characteristics Resolution Absolute Accuracy Unit Resistor Value (R)* Settling Time(1)* Min VDD/24 -- -- -- -- Typ -- -- -- 2k -- Max VDD/32 1/2 1/2 -- 10 Units LSb LSb LSb s Low Range (VRR = 1) High Range (VRR = 0) Comments
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'.
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FIGURE 26-4: LOW-VOLTAGE DETECT CHARACTERISTICS
VDD (LVDIF can be cleared in software)
VLVD (LVDIF set by hardware)
LVDIF
TABLE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic LVD Voltage on VDD Transition High to Low PIC18LF2X20/4X20 LVDL<3:0> = 0000 LVDL<3:0> = 0001 LVDL<3:0> = 0010 LVDL<3:0> = 0011 LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Min Industrial N/A N/A 2.15 2.33 2.43 2.63 2.73 2.91 3.20 3.39 3.49 3.68 3.87 4.06 4.37 Industrial 3.68 3.87 4.06 4.37 Extended 3.48 3.66 3.85 4.14 3.87 4.07 4.28 4.60 4.25 4.48 4.70 5.05 V V V V 3.87 4.07 4.28 4.60 4.07 4.28 4.49 4.82 V V V V N/A N/A 2.26 2.45 2.55 2.77 2.87 3.07 3.36 3.57 3.67 3.87 4.07 4.28 4.60 N/A N/A 2.37 2.58 2.68 2.91 3.01 3.22 3.53 3.75 3.85 4.07 4.28 4.49 4.82 V V V V V V V V V V V V V V V Reserved Reserved Typ Max Units Conditions
PIC18LF2220/2320/4220/4320 (Industrial) PIC18F2220/2320/4220/4320 (Industrial, Extended) Param No. D420 Symbol
D420
LVD Voltage on VDD Transition High to Low PIC18F2X20/4X20 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110
D420E
LVD Voltage on VDD Transition High to Low PIC18F2X20/4X20 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110
Legend:
Shading of rows is to assist in readability of the table. Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
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26.4
26.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid High-impedance High Low
SU STO
Setup Stop condition
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26.4.2 TIMING CONDITIONS
Note: The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-5 specifies the load conditions for the timing specifications. Because of space limitations, the generic terms "PIC18FXX20" and "PIC18LFXX20" are used throughout this section to refer to the PIC18F2220/2320/4220/4320 and PIC18LF2220/2320/4220/4320 families of devices specifically and only those devices.
TABLE 26-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 26.1 and Section 26.3. LF parts operate up to industrial temperatures only.
AC CHARACTERISTICS
FIGURE 26-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load Condition 2
RL
Pin
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26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 26-6:
OSC1
1 2 3 3 4 4
CLKO
TABLE 26-6:
Param. No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Oscillator Frequency(1) Min DC DC DC 0.1 4 4 4 5 Max 40 25 4 1 25 10 6.25 33 -- -- -- -- 250 250 250 -- -- -- -- -- -- 20 50 7.5 Units MHz MHz MHz MHz MHz MHz MHz kHz ns ns ns s ns ns ns s ns ns ns s ns ns ns ns Conditions EC, ECIO (industrial) EC, ECIO (extended) RC osc XT osc HS osc HS + PLL osc (industrial) HS + PLL osc (extended) LP Osc mode EC, ECIO (industrial) EC, ECIO (extended) RC osc XT osc HS osc HS + PLL osc (industrial) HS + PLL osc (extended) LP osc TCY = 4/FOSC (industrial) TCY = 4/FOSC (extended) XT osc LP osc HS osc XT osc LP osc HS osc
Symbol FOSC
1
TOSC
External CLKI
Period(1)
25 40 250 1 40 100 160 30
Oscillator Period(1)
2 3
TCY TOSL, TOSH
Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time
100 160 30 2.5 10 -- -- --
4
TOSR, TOSF
External Clock in (OSC1) Rise or Fall Time
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
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TABLE 26-7:
Param No. F10 F11 F12 F13 Sym
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Characteristic Min 4 16 -- -2 Typ -- -- -- -- Max 10 40 2 +2 Units Conditions
FOSC Oscillator Frequency Range FSYS tPLL CLK On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter)
MHz HS mode only MHz HS mode only ms %
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 26-8:
PIC18LF1220/1320 (Industrial)
INTERNAL RC ACCURACY: PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC18F1220/1320 (Industrial, Extended) Param No. Device
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) F14 F15 F16 F17 F18 F19 F20 F21 Legend: Note 1: 2: 3: INTRC Accuracy @ Freq = 31 kHz PIC18F2220/2320/4220/4320 PIC18LF2220/2320/4220/4320 -2 -5 -10 -2 -5 -10
(2)
+/-1 -- -- +/-1 -- -- -- --
2 5 10 2 5 10 35.938 35.938
% % % % % % kHz kHz
+25C
VDD = 2.7-3.3V
-10C to +85C VDD = 2.7-3.3V -40C to +85C VDD = 2.7-3.3V +25C VDD = 4.5-5.5V -10C to +85C VDD = 4.5-5.5V -40C to +85C VDD = 4.5-5.5V -40C to +85C VDD = 2.7-3.3V -40C to +85C VDD = 4.5-5.5V
PIC18LF2220/2320/4220/4320 26.562 PIC18F2220/2320/4220/4320 26.562
Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration. Change of INTRC frequency as VDD changes.
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FIGURE 26-7: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Refer to Figure 26-5 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3
Note:
TABLE 26-9:
Param No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A Note 1: TIOF
CLKO AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- -- -- Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) (1) (1) (1) (1) (1)
Symbol
TOSH2CKL OSC1 to CLKO TOSH2CKH OSC1 to CLKO TCKR TCKF CLKO Rise Time CLKO Fall Time
TCKL2IOV CLKO to Port Out Valid TIOV2CKH Port In Valid before CLKO TCKH2IOI TOSH2IOI Port In Hold after CLKO OSC1 (Q2 cycle) to Port PIC18FXX20 Input Invalid PIC18LFXX20 (I/O in hold time) Port Output Rise Time Port Output Fall Time PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) TIOR
Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
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FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 26-5 for load conditions. 32 30
31
34
FIGURE 26-9:
VDD
BROWN-OUT RESET TIMING
BVDD 35 VBGAP = 1.2V
VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Param. Symbol No. 30 31 32 33 34 35 36 37 TMCL TWDT TOST TPWRT TIOZ TBOR TIVRST TLVD Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Low-Voltage Detect Pulse Width Min 2 3.48 1024 TOSC 57.0 -- 200 -- 200 Typ -- 4.00 -- 65.5 2 -- 20 -- Max -- 4.71 1024 TOSC 77.2 -- -- 50 -- Units s ms -- ms s s s s VDD VLVD VDD BVDD (see D005) TOSC = OSC1 period Conditions
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FIGURE 26-10:
T0CKI
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
40
41
42 T1OSO/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 26-5 for load conditions.
48
TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param Symbol No. 40 41 42 TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or TCY + 40 N 0.5 TCY + 20 10 25 30 50 0.5 TCY + 5 10 25 30 50 Greater of: 20 ns or TCY + 40 N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
TT1H
T1CKI Synchronous, no prescaler High Time Synchronous, PIC18FXX20 with prescaler PIC18LFXX20 Asynchronous PIC18FXX20 PIC18LFXX20
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46
TT1L
T1CKI Low Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20
47
TT1P
T1CKI Input Period
Synchronous
Asynchronous FT1 48 T1CKI Oscillator Input Frequency Range TCKE2TMRI Delay from External T1CKI Clock Edge to Timer Increment
-- 50 7 TOSC
ns kHz --
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FIGURE 26-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx (Capture Mode)
50 52
51
CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 26-5 for load conditions. 54
TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param Symbol No. 50 TCCL CCPx Input Low Time Characteristic No prescaler With prescaler PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N PIC18FXX20 PIC18LFXX20 54 TCCF CCPx Output Fall Time PIC18FXX20 PIC18LFXX20 -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51
TCCH
CCPx Input High Time
No prescaler With prescaler
52 53
TCCP TCCR
CCPx Input Period CCPx Output Fall Time
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FIGURE 26-12:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC18F4X20)
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 26-5 for load conditions.
64
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
Param. No. 62 63 64 65 66 Symbol Characteristic Min 20 20 35 -- 10 -- Max -- -- -- 80 30 3 TCY Units ns ns ns ns ns Conditions
TDTV2WRH Data in valid before WR or CS (setup time) TWRH2DTI WR or CS to data-in invalid PIC18FXX20 (hold time) PIC18LFXX20 RD or CS to data-out invalid Inhibit of the IBF flag bit being cleared from WR or CS
TRDL2DTV RD and CS to data-out valid TRDH2DTI TIBFINH
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FIGURE 26-13:
SS 70 SCK (CKP = 0) 71 72 78 SCK (CKP = 1) 79 78 79
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 26-5 for load conditions. bit 6 - - - -1
bit 6 - - - - - -1
LSb
LSb In
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param No. 70 71 71A 72 72A 73 73A 74 75 76 78 79 80 Note 1: 2: TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF TSCL Symbol TSSL2SCH, TSSL2SCL TSCH Characteristic SS to SCK or SCK Input SCK Input High Time (Slave mode) SCK Input Low Time (Slave mode) Continuous Single Byte Continuous Single Byte Min TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 -- -- -- -- -- Max Units -- -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions
Setup Time of SDI Data Input to SCK Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDI Data Input to SCK Edge SDO Data Output Rise Time SDO Data Output Fall Time SCK Output Rise Time (Master mode) PIC18FXX20 PIC18LFXX20
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after TSCL2DOV SCK Edge
Requires the use of Parameter # 73A. Only if Parameter # 71A and # 72A are used.
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FIGURE 26-14:
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SDO
MSb 75, 76
bit 6 - - - - - -1
LSb
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param. No. 71 71A 72 72A 73 73A 74 75 76 78 79 80 81 Note 1: 2: TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF TSCL Symbol TSCH Characteristic SCK Input High Time (Slave mode) SCK Input Low Time (Slave mode) Continuous Single Byte Continuous Single Byte Min 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- PIC18FXX20 PIC18LFXX20 -- -- TCY PIC18FXX20 PIC18LFXX20 -- Max Units -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions
Setup Time of SDI Data Input to SCK Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDI Data Input to SCK Edge SDO Data Output Rise Time SDO Data Output Fall Time SCK Output Rise Time (Master mode) PIC18FXX20 PIC18LFXX20
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after TSCL2DOV SCK Edge
TDOV2SCH, SDO Data Output Setup to SCK Edge TDOV2SCL Requires the use of Parameter # 73A. Only if Parameter # 71A and # 72A are used.
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FIGURE 26-15:
SS 70 SCK (CKP = 0) 71 72 83
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
78
79
SCK (CKP = 1) 80 SDO MSb 75, 76 SDI 73 Note: Refer to Figure 26-5 for load conditions. MSb In 74 bit 6 - - - -1 LSb In 79 bit 6 - - - - - -1 78 LSb 77
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param No. 70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 Note 1: 2: TSCL SCK Input Low Time (Slave mode) Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte TDIV2SCH, Setup Time of SDI Data Input to SCK Edge TDIV2SCL TB2B TSCH2DIL, Hold Time of SDI Data Input to SCK Edge TSCL2DIL TDOR TDOF TSCR TSCF SDO Data Output Rise Time SDO Data Output Fall Time SCK Output Rise Time (Master mode) SCK Output Fall Time (Master mode) PIC18FXX20 PIC18LFXX20 -- -- 1.5 TCY + 40 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20 TSCL2DOV PIC18LFXX20 TscH2ssH, SS after SCK Edge TscL2ssH Requires the use of Parameter # 73A. Only if Parameter # 71A and # 72A are used. PIC18FXX20 PIC18LFXX20 -- 10 -- TSSH2DOZ SS to SDO Output High-Impedance 1.25 TCY + 30 40 1.25 TCY + 30 40 100 Max Units Conditions -- -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1)
TSSL2SCH, SS to SCK or SCK Input TSSL2SCL TSCH SCK Input High Time (Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 100 --
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FIGURE 26-16:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
bit 6 - - - - - -1
LSb 77
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param No. 70 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83 Note 1: 2: TB2B TSCL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25 TCY + 30 40 1.25 TCY + 30 40 100 -- -- 10 -- -- -- -- -- -- -- 1.5 TCY + 40 PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 Max Units Conditions -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 1)
TSSL2SCH, SS to SCK or SCK Input TSSL2SCL TSCH SCK Input High Time (Slave mode) SCK Input Low Time (Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge TSCL2DIL TDOR TDOF TSCR TSCF SDO Data Output Rise Time SDO Data Output Fall Time SCK Output Rise Time (Master mode) PIC18FXX20 PIC18LFXX20 TSSH2DOZ SS to SDO Output High-Impedance
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK TSCL2DOV Edge
TSSL2DOV SDO Data Output Valid after SS PIC18FXX20 Edge PIC18LFXX20 TscH2ssH, SS after SCK edge TscL2ssH Requires the use of Parameter # 73A. Only if Parameter # 71A and # 72A are used.
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FIGURE 26-17: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
Start Condition
Stop Condition
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-18: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Setup time Start condition Hold time Stop condition Setup time THD:STO Stop condition Hold time Characteristic Start condition 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
FIGURE 26-18:
I2C BUS DATA TIMING
103 100 101 102
SCL
90 91 106 107 92
SDA In
110 109 109
SDA Out Note: Refer to Figure 26-5 for load conditions.
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TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param. Symbol No. 100 THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode SSP module 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode SSP module 102 103 90 91 106 107 92 109 110 D102 TR TF SDA and SCL Rise Time SDA and SCL Fall Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated CB is specified to be from 10 to 400 pF s s PIC18FXX20 must operate at a minimum of 1.5 MHz PIC18FXX20 must operate at a minimum of 10 MHz Units s s Conditions PIC18FXX20 must operate at a minimum of 1.5 MHz PIC18FXX20 must operate at a minimum of 10 MHz
TSU:STA Start Condition Setup 100 kHz mode Time 400 kHz mode THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 400 kHz mode TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode
THD:DAT Data Input Hold Time 100 kHz mode
TSU:STO Stop Condition Setup 100 kHz mode Time 400 kHz mode TAA TBUF CB Output Valid from Clock Bus Free Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Bus Capacitive Loading
Note 1: 2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released.
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FIGURE 26-19: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL 90 SDA
91 92
93
Start Condition Note: Refer to Figure 26-5 for load conditions.
Stop Condition
TABLE 26-20: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param. Symbol No. 90 TSU:STA Characteristic Start condition Setup time 91 THD:STA Start condition Hold time 92 TSU:STO Stop condition Setup time 93 THD:STO Stop condition Hold time Note 1: 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) Maximum pin capacitance = 10 pF for all Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) I2C pins. Max -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns After this period, the first clock pulse is generated Units ns Conditions Only relevant for Repeated Start condition
FIGURE 26-20:
MASTER SSP I2C BUS DATA TIMING
103 100 101 102
SCL SDA In
90
91
106
107
92
109
109
110
SDA Out Note: Refer to Figure 26-5 for load conditions.
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TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS
Param. Symbol No. 100 THIGH Characteristic Clock High Time Min Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF Time the bus must be free before a new transmission can start (Note 2) After this period, the first clock pulse is generated Only relevant for Repeated Start condition CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Conditions
100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1)
101
TLOW
Clock Low Time
100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1)
102
TR
SDA and SCL Rise Time
100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1)
-- 20 + 0.1 CB -- -- 20 + 0.1 CB --
103
TF
SDA and SCL Fall Time
90
TSU:STA
Start Condition Setup Time
100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1) 100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 0 0 TBD 250 100 TBD
91
THD:STA Start Condition Hold Time
106
THD:DAT Data Input Hold Time
107
TSU:DAT
Data Input Setup Time
92
TSU:STO Stop Condition Setup Time
100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 TBD --
2C
109
TAA
Output Valid from Clock
100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1)
110
TBUF
Bus Free Time
D102 Note 1: 2:
CB
Bus Capacitive Loading
Maximum pin capacitance = 10 pF for all I pins. A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released.
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FIGURE 26-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin 120 Note:
121
121
122
Refer to Figure 26-5 for load conditions.
TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Symbol Characteristic Min Max Units Conditions
TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid TCKRF TDTRF Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time
PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20
-- -- -- -- -- --
40 100 20 50 20 50
ns ns ns ns ns ns
121 122
FIGURE 26-22:
RC6/TX/CK pin RC7/RX/DT pin
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 26-5 for load conditions.
TABLE 26-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. No. 125 126 Symbol Characteristic Min Max Units Conditions
TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) TCKL2DTL Data Hold after CK (DT hold time)
10 15
-- --
ns ns
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TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2220/2320/4220/4320 (INDUSTRIAL) PIC18F2220/2320/4220/4320 (EXTENDED) PIC18LF2220/2320/4220/4320 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A28 A29 A30 A40 A50 NR EIL EDL EOFF EGN -- VREF VREFH VREFL VAIN AVDD AVSS ZAIN IAD IREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Analog Supply Voltage Analog Supply Voltage Recommended Impedance of Analog Voltage Source A/D Current from VDD PIC18FXX20 PIC18LFXX20 3 AVSS + 3.0V AVSS - 0.3V VREFL VDD - 0.3 VSS - 0.3 -- -- -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- guaranteed -- -- -- -- -- -- -- -- -- -- --
(2)
Max 10 <1 <1 <1 <1 AVDD - AVSS AVDD + 0.3V AVDD - 3.0V VREFH VDD + 0.3 VSS + 0.3 2.5(4) 180(5) 90(5) 5(5) 150(5)
Units bit
Conditions VREF 3.0V
LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V V V V k A A A A Average current during conversion(1) During VAIN acquisition. During A/D conversion cycle. Tie to VDD Tie to VSS For 10-bit resolution For 10-bit resolution For 10-bit resolution
VREF Input Current (3)
Note 1: 2: 3: 4: 5:
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. Assume quiet environment. If adjacent pins have high-frequency signals (analog or digital), ZAIN may need to be reduced to as low as 1 k to fight crosstalk effects. For guidance only.
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FIGURE 26-23: A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 130 A/D CLK 132 131
A/D DATA
9
8
7
...
...
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
TCY
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 TAD Characteristic A/D Clock Period PIC18FXX20 PIC18LFXX20 PIC18FXX20 PIC18LFXX20 131 Note 1: 2: TCNV Conversion Time (not including acquisition time)(1) Min 1.6 3.0 2.0 3.0 11 Max 20(2) 20
(2)
Units s s s s TAD
Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode
6.0 9.0 12
ADRES register may be read on the following TCY cycle. The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
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27.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 27-1:
0.5
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
0.4
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 0.3 IDD (mA) 4.5V
4.0V 0.2 3.5V 3.0V
0.1
2.5V 2.0V
0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 27-2:
0.7
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +85C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
0.6
0.5
4.5V 0.4 IDD (mA) 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V 0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
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FIGURE 27-3:
0.7
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
0.6
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
0.5
4.5V 0.4 IDD (mA) 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V
0.0 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 27-4:
2.0
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
1.8
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1.6 5.5V 1.4 5.0V 1.2 IDD (mA) 4.5V 1.0 4.0V 3.5V 3.0V 0.6 2.5V 0.4 2.0V
0.8
0.2
0.0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
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FIGURE 27-5:
2.5
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
2.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V 1.5 IDD (mA) 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V
0.0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
FIGURE 27-6:
16
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25C
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
12 5.0V 10 4.5V IDD (mA) 8 4.0V 6 3.5V 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40
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FIGURE 27-7:
16
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40C TO +125C
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
12 4.0V 10 4.5V IDD (mA) 8
6
3.5V
4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40
FIGURE 27-8:
0.035
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25C
0.030
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 0.025 4.5V
0.020 IDD (mA)
4.0V 3.5V
0.015 3.0V 2.5V 2.0V
0.010
0.005
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
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FIGURE 27-9:
0.045
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +85C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.040
0.035 5.0V 0.030 4.5V IDD (mA) 0.025 4.0V 0.020 3.5V 0.015 3.0V 2.5V 0.010 2.0V
0.005
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
FIGURE 27-10:
0.100
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
0.090
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.080 5.0V
0.070
0.060 IDD (mA)
4.5V 4.0V 3.5V 3.0V
0.050
0.040
0.030 2.5V 0.020 2.0V
0.010
0.000 0.00
0.02
0.04
0.06
0.08
0.10 FOSC (MHz)
0.12
0.14
0.16
0.18
0.20
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FIGURE 27-11:
600
TYPICAL IDD vs. FOSC OVERVVDD PRI_IDLE, EC MODE, +25C Typical I vs F over PRI_IDLE, EC mode, +25C
500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
400 4.5V IDD (A) 4.0V 3.5V 3.0V 200 2.5V 2.0V 100
300
0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
FIGURE 27-12:
600
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
5.0V 400 4.5V 4.0V 300 3.5V
IDD (A)
3.0V 200 2.5V 2.0V 100
0 1.0 1.5 2.0 2.5 FOSC (MHz) 3.0 3.5 4.0
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FIGURE 27-13:
6.0 5.5 5.0 4.5 5.5V 4.0 3.5 IDD (mA) 4.5V 3.0 2.5 4.0V 2.0 1.5 1.0 3.0V 0.5 2.0V 0.0 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40 2.5V 3.5V 5.0V
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
FIGURE 27-14:
6.0 5.5 5.0 4.5 4.0
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40C TO +125C
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V 5.0V
4.5V 3.5 IDD (mA) 3.0 4.0V 2.5 2.0 3.5V 1.5 1.0 3.0V 0.5 0.0 4 8 2.0V 2.5V 12 16 20 FOSC (MHz) 24 28 32 36 40
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FIGURE 27-15:
3000
TYPICAL IPD vs. VDD (+25C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2500
8 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
2000
IPD (A)
1500
4 MHz
1000
2 MHz
500
1 MHz 125 kHz
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-16:
3500
MAXIMUM IPD vs. VDD (-40C TO +125C), 125 kHz TO 8 MHz RC_RUN, ALL PERIPHERALS DISABLED
3000 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
8 MHz
2500
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2000 IPD (A)
4 MHz 1500
1000
2 MHz
500
1 MHz 125 kHz
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 27-17:
100
TYPICAL AND MAXIMUM IPD vs. VDD (-40C TO +125C), 31.25 kHz RC_RUN, ALL PERIPHERALS DISABLED
Max (+125C) Max (+85C) Typ (+25C) IPD (A)
10
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 27-18:
800 750 700 650 600 550 500
TYPICAL IPD vs. VDD (+25C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED
250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves.
8 MHz
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
4 MHz 2 MHz 1 MHz 125 kHz
IPD (A)
450 400 350 300 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
VDD (V)
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FIGURE 27-19:
800 750 700 650 600 550 500 IPD (A) 450 400 350 300 250 200 150 100 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. 8 MHz
MAXIMUM IPD vs. VDD (-40C TO +125C), 125 kHz TO 8 MHz RC_IDLE, ALL PERIPHERALS DISABLED
4 MHz 2 MHz 1 MHz 125 kHz
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
FIGURE 27-20:
100
TYPICAL AND MAXIMUM IPD vs. VDD (-40C TO +125C), 31.25 kHz RC_IDLE, ALL PERIPHERALS DISABLED
Max (+125C)
IPD (A)
Max (+85C) 10 Typ (+25C)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 27-21:
80
IPD SEC_RUN MODE, -10C TO +70C 32.768 kHz XTAL 2 X 22 pF, ALL PERIPHERALS DISABLED
70
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
60 Max (+70C) 50
IPD (A)
40 Typ (+25C)
30
20
10
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-22:
20
IPD SEC_IDLE, -10C TO +70C 32.768 kHz 2 X 22 pF, ALL PERIPHERALS DISABLED
18
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
16
14 Max (+70C) 12
IPD (A)
10 Typ (+25C) 8
6
4
2
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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FIGURE 27-23:
100 Max (+125C)
TOTAL IPD, -40C TO +125C SLEEP MODE, ALL PERIPHERALS DISABLED
10 Max (+85C)
1
IPD (A)
0.1
Typ (+25C) 0.01
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-24:
3.0
VOH vs. IOH OVER TEMPERATURE (-40C TO +125C), VDD = 3.0V
2.5
2.0 Max (+125C) VOH (V) 1.5 Typ (+25C) Min (+125C) 1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
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FIGURE 27-25:
5.0
VOH vs. IOH OVER TEMPERATURE (-40C TO +125C), VDD = 5.0V
4.5 Max (+125C) 4.0 Typ (+25C) 3.5
3.0 VOH (V)
2.5 Min (+125C) 2.0
1.5
1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
FIGURE 27-26:
3.0
VOL vs. IOL OVER TEMPERATURE (-40C TO +125C), VDD = 3.0V V vs I over Temp (-40C to +125C) V = 3.0V
Max (+125C) 2.5
2.0
Max (+85C)
VOL (V)
1.5
Typ (+25C) 1.0
0.5 Min (+125C)
0.0 0 5 10 IOL (-mA) 15 20 25
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FIGURE 27-27:
1.0
VOL vs. IOL OVER TEMPERATURE (-40C TO +125C), VDD = 5.0V
0.9 Max (+125C) 0.8
0.7
0.6 Max (+85C) VOL (V) 0.5
0.4 Typ (+25C) 0.3
0.2 Min (+125C) 0.1
0.0 0 5 10 IOL (-mA) 15 20 25
FIGURE 27-28:
IPD TIMER1 OSCILLATOR, -10C TO +70C SLEEP MODE, TMR1 COUNTER DISABLED SLEEP mode, TMR1 counter disabled IPD Timer1 Oscillator, -10C to +70C
5.0
4.5 Max (-10C to +70C) 4.0
3.5
3.0 Typ (+25C)
IPD (A)
2.5
2.0
1.5
1.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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FIGURE 27-29:
4.5
IPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE, EC OSCILLATOR AT 32 kHz, -40C TO +125C
4.0 Max (-40C) 3.5
3.0
IPD (A)
2.5 Typ (+25C) 2.0
1.5
1.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 27-30:
14
IPD WDT, -40C TO +125C SLEEP MODE, ALL PERIPHERALS DISABLED
12
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
10 Max (+125C)
IPD (A)
8
6 Max (+85C) 4 Typ (+25C)
2
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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FIGURE 27-31:
50
IPD LVD vs. VDD SLEEP MODE, LVD = 2.00V-2.12V
45
40
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Max (+125C)
35 Max (+85C) 30 IPD (A) Typ (+25C)
25
20
15
10 Low-Voltage Detection Range 5 Normal Operating Range 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-32:
40
IPD BOR vs. VDD, -40C TO +125C SLEEP MODE, BOR ENABLED AT 2.00V-2.16V
35
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Max (+125C)
30
25 Typ (+25C)
IPD (A)
20
15
10 Device may be in Reset 5 Device is Operating 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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FIGURE 27-33:
10
IPD A/D, -40C TO +125C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
Max (+125C)
1
IPD (A)
Max (+85C) 0.1
0.01
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Typ (+25C)
0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-34:
5.0
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE, C = 20 pF, TEMPERATURE = +25C
Operation above 4 MHz is not recomended 4.5
4.0 5.1K 3.5
3.0 Freq (MHz)
2.5 10K 2.0
1.5
1.0 33K 0.5 100K 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 27-35:
2.0
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE, C = 100 pF, TEMPERATURE = +25C
1.8
1.6 5.1K 1.4
1.2 Freq (MHz)
1.0 10K 0.8
0.6
0.4 33K 0.2 100K 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 27-36:
0.8
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE, C = 300 pF, TEMPERATURE = +25C
0.7
0.6
0.5 Freq (MHz) 5.1K 0.4
0.3 10K 0.2
0.1
33K 100K
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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28.0
28.1
PACKAGING INFORMATION
Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2220-I/SP 0310017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2320-E/SO 0310017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F4220-I/P 0310017
Legend: XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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Package Marking Information (Continued)
44-Lead TQFP Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4320 -I/PT 0310017
44-Lead QFN
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4220 -I/ML 0310017
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28.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
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28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
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40-Lead Plastic Dual In-line (P) - 600 mil (PDIP)
E1
D
n E
2 1
A c eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
A2 L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15
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44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 A2
MIN
MAX
MIN
MAX
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
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44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
E EXPOSED METAL PAD
p
D D2
2 1 OPTIONAL PIN 1 INDEX ON TOP MARKING PIN 1 INDEX ON EXPOSED PAD (PROFILE MAY VARY) n
B
E2 L
TOP VIEW
BOTTOM VIEW
DETAIL: CONTACT VARIANTS
A1 (A3)
Units Dimension Limits n Number of Contacts p Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length A A1 (A3) E E2 D D2 B L
A
MIN
.031 .000 .309 .246 .309 .246 .008 .014
INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 .268 .315 .268 .013 .016
MAX
1
MIN
.039 .002
2
.321 .274 .321 .274 .013 .019
MILLIMETERS* NOM 44 0.65 BSC 1 0.80 0.90 0 0.02 0.25 REF 2 7.85 8.00 6.25 6.80 7.85 8.00 6.25 6.80 0.20 0.33 0.35 0.40
MAX
1.00 0.05 8.15 6.95 8.15 6.95 0.35 0.48
*Controlling Parameter Notes: 1. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M 2. REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M 3. Contact profiles may vary. 4. JEDEC equivalent: M0-220
Drawing No. C04-103
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NOTES:
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APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES
Revision A (June 2002)
Original data sheet for PIC18F2X20/4X20 devices.
The differences between the devices listed in this data sheet are shown in Table B-1.
Revision B (October 2002)
This revision includes major changes to Section 2.0 "Oscillator Configurations" and Section 3.0 "Power Managed Modes", updates to the Electrical Specifications in Section 26.0 "Electrical Characteristics" and minor corrections to the data sheet text.
Revision C (October 2003)
This revision includes updates to the Electrical Specifications in Section 26.0 "Electrical Characteristics" and to the DC Characteristics Graphs and Charts in Section 27.0 "DC and AC Characteristics Graphs and Tables" and minor corrections to the data sheet text.
TABLE B-1:
DEVICE DIFFERENCES
PIC18F2220 4096 2048 19 Ports A, B, C, (E) 2 0 No 10 input channels 28-pin SPDIP 28-pin SOIC PIC18F2320 8192 4096 19 Ports A, B, C, (E) 2 0 No 10 input channels 28-pin SPDIP 28-pin SOIC PIC18F4220 4096 2048 20 1 1 Yes 13 input channels 40-pin PDIP 44-pin TQFP 44-pin QFN PIC18F4320 8192 4096 20 1 1 Yes 13 input channels 40-pin PDIP 44-pin TQFP 44-pin QFN
Features Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources I/O Ports Capture/Compare/PWM Modules Enhanced Capture/Compare/ PWM Modules Parallel Communications (PSP) 10-bit Analog-to-Digital Module Packages
Ports A, B, C, D, E Ports A, B, C, D, E
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APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES
This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable
This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available
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APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES
A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442." The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716.
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration." This Application Note is available as Literature Number DS00726.
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NOTES:
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INDEX
A
A/D ................................................................................... 211 A/D Converter Interrupt, Configuring ....................... 215 Acquisition Requirements ........................................ 216 ADCON0 Register .................................................... 211 ADCON1 Register .................................................... 211 ADCON2 Register .................................................... 211 ADRESH Register ............................................ 211, 214 ADRESL Register .................................................... 211 Analog Port Pins, Configuring .................................. 218 Associated Registers ............................................... 220 Automatic Acquisition Time ...................................... 217 Calculating the Minimum Required Acquisition Time ............................................... 216 Configuring the Module ............................................ 215 Conversion Clock (TAD) ........................................... 217 Conversion Status (GO/DONE Bit) .......................... 214 Conversions ............................................................. 219 Converter Characteristics ........................................ 341 Operation in Power Managed Modes ...................... 218 Special Event Trigger (CCP) ............................ 136, 220 Use of the CCP2 Trigger .......................................... 220 VREF+ and VREF- References .................................. 216 Absolute Maximum Ratings ............................................. 305 AC (Timing) Characteristics ............................................. 323 Load Conditions for Device Timing Specifications ....................................... 324 Parameter Symbology ............................................. 323 Temperature and Voltage Specifications ................. 324 Timing Conditions .................................................... 324 Access Bank ...................................................................... 65 ACKSTAT Status Flag ..................................................... 185 ADCON0 Register ............................................................ 211 GO/DONE Bit ........................................................... 214 ADCON1 Register ............................................................ 211 ADCON2 Register ............................................................ 211 ADDLW ............................................................................ 261 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART. ADDWF ............................................................................ 261 ADDWFC ......................................................................... 262 ADRESH Register ............................................................ 211 ADRESL Register .................................................... 211, 214 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 262 ANDWF ............................................................................ 263 Assembler MPASM Assembler .................................................. 299 Compare Mode Operation ....................................... 136 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 44 Fail-Safe Clock Monitor ........................................... 248 Generic I/O Port Operation ...................................... 101 Interrupt Logic ............................................................ 88 Low-Voltage Detect (LVD) ....................................... 232 Low-Voltage Detect (LVD) with External Input ........ 232 MCLR/VPP/RE3 Pin ................................................. 111 MSSP (I2C Master Mode) ........................................ 179 MSSP (I2C Mode) .................................................... 164 MSSP (SPI Mode) ................................................... 155 On-Chip Reset Circuit ................................................ 43 PIC18F2220/2320 ....................................................... 9 PIC18F4220/4320 ..................................................... 10 PLL ............................................................................ 20 PORTC (Peripheral Output Override) ...................... 107 PORTD and PORTE (Parallel Slave Port) ............... 114 PWM (Enhanced) .................................................... 143 PWM (Standard) ...................................................... 138 RA3:RA0 and RA5 Pins ........................................... 102 RA4/T0CKI Pin ........................................................ 102 RA6 Pin ................................................................... 102 RA7 Pin ................................................................... 102 RB2:RB0 Pins .......................................................... 105 RB3/CCP2 Pin ......................................................... 105 RB4 Pin ................................................................... 105 RB7:RB5 Pins .......................................................... 104 RD4:RD0 Pins ......................................................... 110 RD7:RD5 Pins ......................................................... 109 RE2:RE0 Pins .......................................................... 111 Reads from Flash Program Memory .......................... 75 System Clock ............................................................. 25 Table Read Operation ............................................... 71 Table Write Operation ................................................ 72 Table Writes to Flash Program Memory .................... 77 Timer0 in 16-bit Mode .............................................. 118 Timer0 in 8-bit Mode ................................................ 118 Timer1 ..................................................................... 122 Timer1 (16-bit Read/Write Mode) ............................ 122 Timer2 ..................................................................... 128 Timer3 ..................................................................... 130 Timer3 (16-bit Read/Write Mode) ............................ 130 USART Receive ....................................................... 204 USART Transmit ...................................................... 202 Watchdog Timer ...................................................... 245 BN .................................................................................... 264 BNC ................................................................................. 265 BNN ................................................................................. 265 BNOV ............................................................................... 266 BNZ .................................................................................. 266 BOR. See Brown-out Reset. BOV ................................................................................. 269 BRA ................................................................................. 267 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..............................................44, 237 BSF .................................................................................. 267 BTFSC ............................................................................. 268 BTFSS ............................................................................. 268 BTG ................................................................................. 269 BZ .................................................................................... 270
B
Bank Select Register (BSR) ............................................... 65 Baud Rate Generator ....................................................... 181 BC .................................................................................... 263 BCF .................................................................................. 264 BF Status Flag ................................................................. 185 Block Diagrams A/D ........................................................................... 214 Analog Input Model .................................................. 215 Baud Rate Generator ............................................... 181 Capture Mode Operation ......................................... 135 Comparator I/O Operating Modes ............................ 222 Comparator Output .................................................. 224 Comparator Voltage Reference ............................... 228
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C
C Compilers MPLAB C17 ............................................................. 300 MPLAB C18 ............................................................. 300 MPLAB C30 ............................................................. 300 CALL ................................................................................ 270 Capture (CCP Module) ..................................................... 135 Associated Registers ............................................... 137 CCP Pin Configuration ............................................. 135 CCPR1H:CCPR1L Registers ................................... 135 Software Interrupt ..................................................... 135 Timer1/Timer3 Mode Selection ................................ 135 Capture (ECCP Module) .................................................. 142 Capture/Compare/PWM (CCP) ........................................ 133 Capture Mode. See Capture. CCP1 ........................................................................ 134 CCPR1H Register ............................................ 134 CCPR1L Register ............................................ 134 CCP2 ........................................................................ 134 CCPR2H Register ............................................ 134 CCPR2L Register ............................................ 134 Compare Mode. See Compare. Interaction of Two CCP Modules ............................. 134 PWM Mode. See PWM. Timer Resources ...................................................... 134 Clock Sources .................................................................... 24 Selection Using OSCCON Register ........................... 24 Clocking Scheme/Instruction Cycle .................................... 57 CLRF ................................................................................ 271 CLRWDT .......................................................................... 271 Code Examples 16 x 16 Signed Multiply Routine ................................. 86 16 x 16 Unsigned Multiply Routine ............................. 86 8 x 8 Signed Multiply Routine ..................................... 85 8 x 8 Unsigned Multiply Routine ................................. 85 Changing Between Capture Prescalers ................... 135 Computed GOTO Using an Offset Value ................... 59 Data EEPROM Read ................................................. 83 Data EEPROM Refresh Routine ................................ 84 Data EEPROM Write .................................................. 83 Erasing a Flash Program Memory Row ..................... 76 Fast Register Stack .................................................... 56 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 66 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 125 Initializing PORTA .................................................... 101 Initializing PORTB .................................................... 104 Initializing PORTC .................................................... 107 Initializing PORTD .................................................... 109 Initializing PORTE .................................................... 111 Loading the SSPBUF (SSPSR) Register ................. 158 Reading a Flash Program Memory Word ................... 75 Saving Status, WREG and BSR Registers in RAM ............................................................... 99 Writing to Flash Program Memory ....................... 78-79 Code Protection ....................................................... 237, 251 COMF ............................................................................... 272 Comparator ...................................................................... 221 Analog Input Connection Considerations ................ 225 Associated Registers ............................................... 226 Configuration ........................................................... 221 Effects of a Reset .................................................... 225 Interrupts .................................................................. 224 Operation ................................................................. 223 Operation in Power Managed Modes ...................... 225 Outputs .................................................................... 223 Reference ................................................................ 223 Response Time ........................................................ 223 Comparator Specifications ............................................... 321 Comparator Voltage Reference ....................................... 227 Accuracy and Error .................................................. 228 Associated Registers ............................................... 229 Configuring .............................................................. 227 Connection Considerations ...................................... 228 Effects of a Reset .................................................... 228 Operation in Power Managed Modes ...................... 228 Compare (CCP Module) .................................................. 136 Associated Registers ............................................... 137 CCP Pin Configuration ............................................. 136 CCPR1 Register ...................................................... 136 Software Interrupt .................................................... 136 Special Event Trigger .......................................136, 220 Timer1/Timer3 Mode Selection ................................ 136 Compare (ECCP Mode) ................................................... 142 Computed GOTO ............................................................... 59 Configuration Bits ............................................................ 237 Configuration Register Protection .................................... 254 Context Saving During Interrupts ....................................... 99 Control Registers EECON1 and EECON2 ............................................. 72 Conversion Considerations .............................................. 370 CPFSEQ .......................................................................... 272 CPFSGT .......................................................................... 273 CPFSLT ........................................................................... 273 Crystal Oscillator/Ceramic Resonator ................................ 19
D
Data EEPROM Code Protection ...................................... 254 Data EEPROM Memory ..................................................... 81 Associated Registers ................................................. 84 EEADR Register ........................................................ 81 EECON1 and EECON2 Registers ............................. 81 Operation During Code-Protect ................................. 84 Protection Against Spurious Write ............................. 83 Reading ..................................................................... 83 Using .......................................................................... 84 Write Verify ................................................................ 83 Writing ........................................................................ 83 Data Memory ..................................................................... 59 General Purpose Registers ....................................... 59 Map for PIC18F2X20/4X20 ........................................ 60 Special Function Registers ........................................ 61 DAW ................................................................................ 274 DC and AC Characteristics Graphs and Tables .................................................. 343 DC Characteristics ........................................................... 318 Power-Down and Supply Current ............................ 309 Supply Voltage ......................................................... 308 DCFSNZ .......................................................................... 275 DECF ............................................................................... 274 DECFSZ .......................................................................... 275
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Demonstration Boards PICDEM 1 ................................................................ 302 PICDEM 17 .............................................................. 302 PICDEM 18R PIC18C601/801 ................................. 303 PICDEM 2 Plus ........................................................ 302 PICDEM 3 PIC16C92X ............................................ 302 PICDEM 4 ................................................................ 302 PICDEM LIN PIC16C43X ........................................ 303 PICDEM USB PIC16C7X5 ....................................... 303 PICDEM.net Internet/Ethernet ................................. 302 Development Support ...................................................... 299 Device Differences ........................................................... 369 Device Overview .................................................................. 7 Features (table) ............................................................ 8 New Core Features ...................................................... 7 Other Special Features ................................................ 7 Direct Addressing ............................................................... 67
G
GOTO .............................................................................. 276
H
Hardware Multiplier ............................................................ 85 Introduction ................................................................ 85 Operation ................................................................... 85 Performance Comparison .......................................... 85 HSPLL ............................................................................... 20
I
I/O Ports ........................................................................... 101 I2C Mode ACK Pulse ........................................................168, 169 Acknowledge Sequence Timing .............................. 188 Baud Rate Generator .............................................. 181 Bus Collision During a Repeated Start Condition ................................................. 192 Bus Collision During a Start Condition ..................... 190 Bus Collision During a Stop Condition ..................... 193 Clock Arbitration ...................................................... 182 Clock Stretching ....................................................... 174 Effect of a Reset ...................................................... 189 General Call Address Support ................................. 178 Master Mode ............................................................ 179 Master Mode (Reception, 7-bit Address) ................. 187 Master Mode Operation ........................................... 180 Master Mode Reception ........................................... 185 Master Mode Repeated Start Condition Timing .............................................. 184 Master Mode Start Condition Timing ....................... 183 Master Mode Transmission ..................................... 185 Multi-Master Communication, Bus Collision and Bus Arbitration .......................................... 189 Multi-Master Mode ................................................... 189 Operation ................................................................. 168 Operation in Power Managed Mode ........................ 189 Read/Write Bit Information (R/W Bit) ................168, 169 Registers ................................................................. 164 Serial Clock (RC3/SCK/SCL) ................................... 169 Slave Mode .............................................................. 168 Addressing ....................................................... 168 Reception ........................................................ 169 Transmission ................................................... 169 Stop Condition Timing ............................................. 188 ID Locations ..............................................................237, 254 INCF ................................................................................ 276 INCFSZ ............................................................................ 277 In-Circuit Debugger .......................................................... 254 In-Circuit Serial Programming (ICSP) .......................237, 254 Indirect Addressing INDF and FSR Registers ........................................... 66 Operation ................................................................... 66 Indirect Addressing Operation ........................................... 67 Indirect File Operand ......................................................... 59 INFSNZ ............................................................................ 277 Initialization Conditions for all Registers .......................46-49 Instruction Cycle ................................................................ 57 Instruction Flow/Pipelining ................................................. 57 Instruction Format ............................................................ 257
E
ECCP ............................................................................... 141 Auto-Shutdown ........................................................ 149 and Automatic Restart ..................................... 151 Capture and Compare Modes .................................. 142 Outputs .................................................................... 142 Standard PWM Mode ............................................... 142 Start-up Considerations ........................................... 151 Effects of Power Managed Modes on Various Clock Sources ............................................... 27 Electrical Characteristics .................................................. 305 Enhanced Capture/Compare/PWM (ECCP) .................... 141 Capture Mode. See Capture (ECCP Module). PWM Mode. See PWM (ECCP Module). Enhanced CCP Auto-Shutdown ....................................... 149 Enhanced PWM Mode. See PWM (ECCP Module). Equations 16 x 16 Signed Multiplication Algorithm ..................... 86 16 x 16 Unsigned Multiplication Algorithm ................. 86 A/D Acquisition Time ................................................ 216 A/D Minimum Holding Capacitor .............................. 216 Errata ................................................................................... 5 Evaluation and Programming Tools ................................. 303 External Clock Input ........................................................... 21
F
Fail-Safe Clock Monitor ............................................ 237, 248 Interrupts in Power Managed Modes ....................... 250 POR or Wake-up from Sleep ................................... 250 WDT During Oscillator Failure ................................. 248 Fast Register Stack ............................................................ 56 Firmware Instructions ....................................................... 255 Flash Program Memory ...................................................... 71 Associated Registers ................................................. 79 Control Registers ....................................................... 72 Erase Sequence ........................................................ 76 Erasing ....................................................................... 76 Operation During Code-Protect ................................. 79 Reading ...................................................................... 75 TABLAT Register ....................................................... 74 Table Pointer .............................................................. 74 Boundaries Based on Operation ........................ 74 Table Pointer Boundaries .......................................... 74 Table Reads and Table Writes .................................. 71 Unexpected Termination of Write Operation .............. 79 Write Verify ................................................................ 79 Writing to .................................................................... 77 FSCM. See Fail-Safe Clock Monitor.
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Instruction Set .................................................................. 255 ADDLW .................................................................... 261 ADDWF .................................................................... 261 ADDWFC ................................................................. 262 ANDLW .................................................................... 262 ANDWF .................................................................... 263 BC ............................................................................ 263 BCF .......................................................................... 264 BN ............................................................................ 264 BNC .......................................................................... 265 BNN .......................................................................... 265 BNOV ....................................................................... 266 BNZ .......................................................................... 266 BOV .......................................................................... 269 BRA .......................................................................... 267 BSF .......................................................................... 267 BTFSC ..................................................................... 268 BTFSS ...................................................................... 268 BTG .......................................................................... 269 BZ ............................................................................. 270 CALL ........................................................................ 270 CLRF ........................................................................ 271 CLRWDT .................................................................. 271 COMF ....................................................................... 272 CPFSEQ .................................................................. 272 CPFSGT ................................................................... 273 CPFSLT ................................................................... 273 DAW ......................................................................... 274 DCFSNZ ................................................................... 275 DECF ....................................................................... 274 DECFSZ ................................................................... 275 GOTO ....................................................................... 276 INCF ......................................................................... 276 INCFSZ .................................................................... 277 INFSNZ .................................................................... 277 IORLW ..................................................................... 278 IORWF ..................................................................... 278 LFSR ........................................................................ 279 MOVF ....................................................................... 279 MOVFF ..................................................................... 280 MOVLB ..................................................................... 280 MOVLW .................................................................... 281 MOVWF ................................................................... 281 MULLW .................................................................... 282 MULWF .................................................................... 282 NEGF ....................................................................... 283 NOP ......................................................................... 283 POP .......................................................................... 284 PUSH ....................................................................... 284 RCALL ...................................................................... 285 Reset ........................................................................ 285 RETFIE .................................................................... 286 RETLW ..................................................................... 286 RETURN .................................................................. 287 RLCF ........................................................................ 287 RLNCF ..................................................................... 288 RRCF ....................................................................... 288 RRNCF ..................................................................... 289 SETF ........................................................................ 289 SLEEP ...................................................................... 290 SUBFWB .................................................................. 290 SUBLW .................................................................... 291 SUBWF .................................................................... 291 SUBWFB ................................................................. 292 SWAPF .................................................................... 293 TBLRD ..................................................................... 294 TBLWT ..................................................................... 295 TSTFSZ ................................................................... 296 XORLW .................................................................... 296 XORWF ................................................................... 297 Summary Table ....................................................... 258 INTCON Register RBIF Bit ................................................................... 104 INTCON Registers ............................................................. 89 Inter-Integrated Circuit. See I2C. Internal Oscillator Block ..................................................... 22 Adjustment ................................................................. 22 INTIO Modes ............................................................. 22 INTRC Output Frequency .......................................... 22 OSCTUNE Register ................................................... 22 Internal RC Oscillator Use with WDT .......................................................... 245 Interrupt Sources ............................................................. 237 A/D Conversion Complete ....................................... 215 Capture Complete (CCP) ......................................... 135 Compare Complete (CCP) ....................................... 136 Interrupt-on-Change (RB7:RB4) .............................. 104 INTn Pin ..................................................................... 99 PORTB, Interrupt-on-Change .................................... 99 TMR0 ......................................................................... 99 TMR1 Overflow ........................................................ 121 TMR2 to PR2 Match ................................................ 128 TMR2 to PR2 Match (PWM) .............................127, 138 TMR3 Overflow .................................................129, 131 USART Receive/Transmit Complete ....................... 195 Interrupts ............................................................................ 87 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit) ..................................... 135 Interrupts, Flag Bits CCP1 Flag (CCP1IF Bit) .......................................... 135 CCP1IF Flag (CCP1IF Bit) ....................................... 136 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 104 INTOSC Frequency Drift .................................................... 40 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 278 IORWF ............................................................................. 278 IPR Registers ..................................................................... 96
L
LFSR ................................................................................ 279 Look-up Tables .................................................................. 59 Low-Voltage Detect ......................................................... 231 Characteristics ......................................................... 322 Effects of a Reset .................................................... 235 Operation ................................................................. 234 Current Consumption ....................................... 235 Reference Voltage Set Point ........................... 235 Operation During Sleep ........................................... 235 Low-Voltage ICSP Programming ..................................... 254 LVD. See Low-Voltage Detect.
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M
Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 53 Data Memory ............................................................. 59 Program Memory ....................................................... 53 Memory Programming Requirements .............................. 320 Migration from Baseline to Enhanced Devices ................ 370 Migration from High-End to Enhanced Devices ............... 371 Migration from Mid-Range to Enhanced Devices ............. 371 MOVF ............................................................................... 279 MOVFF ............................................................................. 280 MOVLB ............................................................................. 280 MOVLW ............................................................................ 281 MOVWF ........................................................................... 281 MPLAB ASM30 Assembler, Linker, Librarian .................. 300 MPLAB ICD 2 In-Circuit Debugger ................................... 301 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator ................................... 301 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator ................................... 301 MPLAB Integrated Development Environment Software .............................................. 299 MPLINK Object Linker/MPLIB Object Librarian ............... 300 MSSP ............................................................................... 155 Control Registers (General) ..................................... 155 Enabling SPI I/O ...................................................... 159 I2C Master Mode ...................................................... 179 I2C Mode I2C Slave Mode ........................................................ 168 Operation ................................................................. 158 Overview .................................................................. 155 Slave Select Control ................................................ 161 SPI Master Mode ..................................................... 160 SPI Master/Slave Connection .................................. 159 SPI Mode ................................................................. 155 SPI Slave Mode ....................................................... 161 Typical Connection .................................................. 159 MULLW ............................................................................ 282 MULWF ............................................................................ 282 Oscillator Start-up Timer (OST) ............................ 27, 44, 237 Oscillator Switching ........................................................... 24 Oscillator Transitions ......................................................... 27 Oscillator, Timer1 ......................................................121, 131 Oscillator, Timer3 ............................................................. 129
P
Packaging Information ..................................................... 361 Marking .............................................................361, 362 Parallel Slave Port (PSP) ..........................................109, 114 Associated Registers ............................................... 115 CS (Chip Select) ...............................................113, 114 PORTD .................................................................... 114 RD (Read Input) ................................................113, 114 RE0/AN5/RD Pin ..................................................... 113 RE1/AN6/WR Pin ..................................................... 113 RE2/AN7/CS Pin ...................................................... 113 Select (PSPMODE Bit) .....................................109, 114 WR (Write Input) ...............................................113, 114 PICkit 1 Flash Starter Kit ................................................. 303 PICSTART Plus Development Programmer .................... 301 PIE Registers ..................................................................... 94 Pin Functions MCLR/VPP/RE3 ....................................................11, 14 OSC1/CLKI/RA7 ...................................................11, 14 OSC2/CLKO/RA6 .................................................11, 14 RA0/AN0 ...............................................................11, 14 RA1/AN1 ...............................................................11, 14 RA2/AN2/VREF-/CVREF .........................................11, 14 RA3/AN3/VREF+ ...................................................11, 14 RA4/T0CKI/C1OUT ..............................................11, 14 RA5/AN4/SS/LVDIN/C2OUT ................................11, 14 RB0/AN12/INT0 ....................................................12, 15 RB1/AN10/INT1 ....................................................12, 15 RB2/AN8/INT2 ......................................................12, 15 RB3/AN9/CCP2 ....................................................12, 15 RB4/AN11/KBI0 ....................................................12, 15 RB5/KBI1/PGM .....................................................12, 15 RB6/KBI2/PGC .....................................................12, 15 RB7/KBI3/PGD .......................................................... 12 RB7/PGD ................................................................... 15 RC0/T1OSO/T1CKI ..............................................13, 16 RC1/T1OSI/CCP2 .................................................13, 16 RC2/CCP1/P1A ....................................................13, 16 RC3/SCK/SCL ......................................................13, 16 RC4/SDI/SDA .......................................................13, 16 RC5/SDO ..............................................................13, 16 RC6/TX/CK ...........................................................13, 16 RC7/RX/DT ...........................................................13, 16 RD0/PSP0 ................................................................. 17 RD1/PSP1 ................................................................. 17 RD2/PSP2 ................................................................. 17 RD3/PSP3 ................................................................. 17 RD4/PSP4 ................................................................. 17 RD5/PSP5/P1B ......................................................... 17 RD6/PSP6/P1C ......................................................... 17 RD7/PSP7/P1D ......................................................... 17 RE0/AN5/RD .............................................................. 18 RE1/AN6/WR ............................................................. 18 RE2/AN7/CS .............................................................. 18 RE3 ............................................................................ 18 VDD .......................................................................13, 18 VSS .......................................................................13, 18
N
NEGF ............................................................................... 283 NOP ................................................................................. 283
O
Opcode Field Descriptions ............................................... 256 OPTION_REG Register PSA Bit ..................................................................... 119 T0CS Bit ................................................................... 119 T0PS2:T0PS0 Bits ................................................... 119 T0SE Bit ................................................................... 119 Oscillator Configuration ...................................................... 19 EC .............................................................................. 19 ECIO .......................................................................... 19 HS .............................................................................. 19 HSPLL ........................................................................ 19 Internal Oscillator Block ............................................. 22 INTIO1 ....................................................................... 19 INTIO2 ....................................................................... 19 LP ............................................................................... 19 RC .............................................................................. 19 RCIO .......................................................................... 19 XT .............................................................................. 19 Oscillator Selection .......................................................... 237
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Pinout I/O Descriptions PIC18F2220/2320 ...................................................... 11 PIC18F4220/4320 ...................................................... 14 PIR Registers ..................................................................... 92 PLL Lock Time-out ............................................................. 44 Pointer, FSRn ..................................................................... 66 POP .................................................................................. 284 POR. See Power-on Reset. PORTA Associated Registers ............................................... 103 LATA Register .......................................................... 101 PORTA Register ...................................................... 101 TRISA Register ........................................................ 101 PORTB Associated Registers ............................................... 106 LATB Register .......................................................... 104 PORTB Register ...................................................... 104 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 104 TRISB Register ........................................................ 104 PORTC Associated Registers ............................................... 108 LATC Register .......................................................... 107 PORTC Register ...................................................... 107 TRISC Register ........................................................ 107 PORTD Associated Registers ............................................... 110 LATD Register .......................................................... 109 Parallel Slave Port (PSP) Function .......................... 109 PORTD Register ...................................................... 109 TRISD Register ........................................................ 109 PORTE Analog Port Pins ...................................................... 113 Associated Registers ............................................... 113 LATE Register .......................................................... 111 PORTE Register ...................................................... 111 PSP Mode Select (PSPMODE Bit) .......................... 109 RE0/AN5/RD Pin ...................................................... 113 RE1/AN6/WR Pin ..................................................... 113 RE2/AN7/CS Pin ...................................................... 113 TRISE Register ........................................................ 111 Postscaler, WDT Assignment (PSA Bit) ............................................... 119 Rate Select (T0PS2:T0PS0 Bits) ............................. 119 Power Managed Modes ..................................................... 29 Entering ...................................................................... 30 Idle Modes .................................................................. 31 Run Modes ................................................................. 36 Selecting .................................................................... 29 Sleep Mode ................................................................ 31 Summary (table) ......................................................... 29 Wake-up from ............................................................. 38 Power-on Reset (POR) .............................................. 44, 237 Power-up Delays ................................................................ 27 Power-up Timer (PWRT) ...................................... 27, 44, 237 Prescaler, Capture ........................................................... 135 Prescaler, Timer0 ............................................................. 119 Assignment (PSA Bit) ............................................... 119 Rate Select (T0PS2:T0PS0 Bits) ............................. 119 Prescaler, Timer2 ............................................................. 139 PRO MATE II Universal Device Programmer ................... 301 Product Identification System ........................................... 385 Program Counter PCL Register .............................................................. 56 PCLATH Register ....................................................... 56 PCLATU Register ....................................................... 56 Program Memory Instructions ................................................................ 58 Two-Word .......................................................... 58 Interrupt Vector .......................................................... 53 Map and Stack for PIC18F2220/4220 ....................... 53 Map and Stack for PIC18F2320/4320 ....................... 53 Reset Vector .............................................................. 53 Program Memory Code Protection .................................. 252 Program Verification ........................................................ 251 Program Verification and Code Protection Associated Registers ............................................... 251 Programming, Device Instructions ................................... 255 PSP. See Parallel Slave Port. Pulse Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 284 PUSH and POP Instructions .............................................. 55 PWM (CCP Module) ........................................................ 138 Associated Registers ............................................... 139 CCPR1H:CCPR1L Registers ................................... 138 Duty Cycle ............................................................... 138 Example Frequencies/Resolutions .......................... 139 Period ...................................................................... 138 Setup for PWM Operation ........................................ 139 TMR2 to PR2 Match .........................................127, 138 PWM (ECCP Module) ...................................................... 143 Associated Registers ............................................... 153 Direction Change in Full-Bridge Output Mode ......... 147 Effects of a Reset .................................................... 152 Full-Bridge Application Example .............................. 147 Full-Bridge Mode ..................................................... 146 Half-Bridge Mode ..................................................... 145 Half-Bridge Output Mode Applications Example ...... 145 Operation in Power Managed Modes ...................... 152 Operation with Fail-Safe Clock Monitor ................... 152 Output Configurations .............................................. 143 Output Relationships (Active-High State) ................ 144 Output Relationships (Active-Low State) ................. 144 Programmable Dead Band Delay ............................ 149 Setup for Operation ................................................. 152 Shoot-Through Current ............................................ 149 Start-up Considerations ........................................... 151
Q
Q Clock ............................................................................ 139
R
RAM. See Data Memory. RC Oscillator ...................................................................... 21 RCIO Oscillator Mode ................................................ 21 RCALL ............................................................................. 285 RCON Register Bit Status During Initialization .................................... 45 Bits and Positions ...................................................... 45 RCSTA Register SPEN Bit .................................................................. 195 Register File ....................................................................... 59 Registers ADCON0 (A/D Control 0) ......................................... 211 ADCON1 (A/D Control 1) ......................................... 212 ADCON2 (A/D Control 2) ......................................... 213 CCP1CON (Enhanced CCP Operation Control 1) ........................................ 141 CCPxCON (Capture/Compare/PWM Control) ......... 133 CMCON (Comparator Control) ................................ 221 CONFIG1H (Configuration 1 High) .......................... 238
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CONFIG2H (Configuration 2 High) .......................... 239 CONFIG2L (Configuration 2 Low) ............................ 239 CONFIG3H (Configuration 3 High) .......................... 240 CONFIG4L (Configuration 4 Low) ............................ 240 CONFIG5H (Configuration 5 High) .......................... 241 CONFIG5L (Configuration 5 Low) ............................ 241 CONFIG6H (Configuration 6 High) .......................... 242 CONFIG6L (Configuration 6 Low) ............................ 242 CONFIG7H (Configuration 7 High) .......................... 243 CONFIG7L (Configuration 7 Low) ............................ 243 CVRCON (Comparator Voltage Reference Control) ........................................... 227 Device ID Register 1 ................................................ 244 Device ID Register 2 ................................................ 244 ECCPAS (Enhanced CCP Auto-Shutdown Control) ................................... 150 EECON1 (Data EEPROM Control 1) ................... 73, 82 INTCON (Interrupt Control) ........................................ 89 INTCON2 (Interrupt Control 2) ................................... 90 INTCON3 (Interrupt Control 3) ................................... 91 IPR1 (Peripheral Interrupt Priority 1) .......................... 96 IPR2 (Peripheral Interrupt Priority 2) .......................... 97 LVDCON (LVD Control) ........................................... 233 OSCCON (Oscillator Control) .................................... 26 OSCTUNE (Oscillator Tuning) ................................... 23 PIE1 (Peripheral Interrupt Enable 1) .......................... 94 PIE2 (Peripheral Interrupt Enable 2) .......................... 95 PIR1 (Peripheral Interrupt Request (Flag) 1) ............................................................. 92 PIR2 (Peripheral Interrupt Request (Flag) 2) ............................................................. 93 PWM1CON (Enhanced PWM Configuration) ........... 149 RCON (Reset Control) ......................................... 69, 98 RCSTA (Receive Status and Control) ...................... 197 SSPCON1 (MSSP Control 1, I2C Mode) ................. 166 SSPCON1 (MSSP Control 1, SPI Mode) ................. 157 SSPCON2 (MSSP Control 2, I2C Mode) ................. 167 SSPSTAT (MSSP Status, I2C Mode) ....................... 165 SSPSTAT (MSSP Status, SPI Mode) ...................... 156 Status ......................................................................... 68 STKPTR (Stack Pointer) ............................................ 55 Summary .............................................................. 62-64 T0CON (Timer0 Control) .......................................... 117 T1CON (Timer 1 Control) ......................................... 121 T2CON (Timer 2 Control) ......................................... 127 T3CON (Timer3 Control) .......................................... 129 TRISE ...................................................................... 112 TXSTA (Transmit Status and Control) ..................... 196 WDTCON (Watchdog Timer Control) ....................... 246 Reset .......................................................................... 43, 285 Resets .............................................................................. 237 RETFIE ............................................................................ 286 RETLW ............................................................................. 286 RETURN .......................................................................... 287 Return Address Stack ........................................................ 54 Return Stack Pointer (STKPTR) ........................................ 54 Revision History ............................................................... 369 RLCF ................................................................................ 287 RLNCF ............................................................................. 288 RRCF ............................................................................... 288 RRNCF ............................................................................. 289
S
SCI. See USART. SCK ................................................................................. 155 SDI ................................................................................... 155 SDO ................................................................................. 155 Serial Clock (SCK) Pin ..................................................... 155 Serial Communication Interface. See USART. Serial Data In (SDI) Pin ................................................... 155 Serial Data Out (SDO) Pin ............................................... 155 Serial Peripheral Interface. See SPI Mode. SETF ................................................................................ 289 Shoot-Through Current .................................................... 149 Slave Select (SS) Pin ...................................................... 155 SLEEP ............................................................................. 290 Sleep OSC1 and OSC2 Pin States ...................................... 27 Software Simulator (MPLAB SIM) ................................... 300 Software Simulator (MPLAB SIM30) ............................... 300 Special Event Trigger. See Compare (CCP Module) Special Features of the CPU ........................................... 237 Special Function Registers ................................................ 61 Map ............................................................................ 61 SPI Mode Associated Registers ............................................... 163 Bus Mode Compatibility ........................................... 163 Effects of a Reset .................................................... 163 Master in Power Managed Modes ........................... 163 Master Mode ............................................................ 160 Master/Slave Connection ......................................... 159 Registers ................................................................. 156 Serial Clock .............................................................. 155 Serial Data In ........................................................... 155 Serial Data Out ........................................................ 155 Slave in Power Managed Modes ............................. 163 Slave Mode .............................................................. 161 Slave Select ............................................................. 155 SPI Clock ................................................................. 160 SS .................................................................................... 155 SSP I2C Mode. See I2C. SSPBUF Register .................................................... 160 SSPSR Register ...................................................... 160 TMR2 Output for Clock Shift .............................127, 128 SSPOV Status Flag ......................................................... 185 SSPSTAT Register R/W Bit .............................................................168, 169 Stack Full/Underflow Resets .............................................. 55 SUBFWB ......................................................................... 290 SUBLW ............................................................................ 291 SUBWF ............................................................................ 291 SUBWFB ......................................................................... 292 SWAPF ............................................................................ 293
T
TABLAT Register ............................................................... 74 Table Pointer Operations (table) ........................................ 74 Table Reads/Table Writes ................................................. 59 TBLPTR Register ............................................................... 74 TBLRD ............................................................................. 294 TBLWT ............................................................................. 295 Time-out in Various Situations (table) ................................ 45 Time-out Sequence ........................................................... 44
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Timer0 .............................................................................. 117 16-bit Mode Timer Reads and Writes ...................... 119 Associated Registers ............................................... 119 Clock Source Edge Select (T0SE Bit) ...................... 119 Clock Source Select (T0CS Bit) ............................... 119 Interrupt .................................................................... 119 Operation ................................................................. 119 Prescaler. See Prescaler, Timer0. Switching Prescaler Assignment .............................. 119 Timer1 .............................................................................. 121 16-bit Read/Write Mode ........................................... 124 Associated Registers ............................................... 125 Interrupt .................................................................... 124 Operation ................................................................. 122 Oscillator .......................................................... 121, 123 Oscillator Layout Considerations ............................. 123 Overflow Interrupt ..................................................... 121 Resetting, Using a Special Event Trigger Output (CCP) ....................................... 124 Special Event Trigger (CCP) .................................... 136 TMR1H Register ...................................................... 121 TMR1L Register ....................................................... 121 Use as a Real-Time Clock ....................................... 124 Timer2 .............................................................................. 127 Associated Registers ............................................... 128 Operation ................................................................. 127 Postscaler. See Postscaler, Timer2. PR2 Register .................................................... 127, 138 Prescaler. See Prescaler, Timer2. SSP Clock Shift ................................................ 127, 128 TMR2 Register ......................................................... 127 TMR2 to PR2 Match Interrupt .................. 127, 128, 138 Timer3 .............................................................................. 129 Associated Registers ............................................... 131 Operation ................................................................. 130 Oscillator .......................................................... 129, 131 Overflow Interrupt ............................................. 129, 131 Resetting, Using a Special Event Trigger Output (CCP) ....................................... 131 TMR3H Register ...................................................... 129 TMR3L Register ....................................................... 129 Timing Diagrams A/D Conversion ........................................................ 342 Acknowledge Sequence ........................................... 188 Asynchronous Reception ......................................... 205 Asynchronous Transmission .................................... 203 Asynchronous Transmission (Back to Back) ............ 203 Baud Rate Generator with Clock Arbitration ............ 182 BRG Reset Due to SDA Arbitration During Start Condition ...................................... 191 Brown-out Reset (BOR) ........................................... 328 Bus Collision During a Repeated Start Condition (Case 1) .................................. 192 Bus Collision During a Repeated Start Condition (Case 2) .................................. 192 Bus Collision During a Stop Condition (Case 1) ........................................................... 193 Bus Collision During a Stop Condition (Case 2) ........................................................... 193 Bus Collision During Start Condition (SCL = 0) .......................................................... 191 Bus Collision During Start Condition (SDA Only) ....................................................... 190 Bus Collision for Transmit and Acknowledge .................................................... 189 Capture/Compare/PWM (CCP) ............................... 330 CLKO and I/O .......................................................... 327 Clock Synchronization ............................................. 175 Clock, Instruction Cycle ............................................. 57 Example SPI Master Mode (CKE = 0) ..................... 332 Example SPI Master Mode (CKE = 1) ..................... 333 Example SPI Slave Mode (CKE = 0) ....................... 334 Example SPI Slave Mode (CKE = 1) ....................... 335 External Clock (All Modes except PLL) ................... 325 Fail-Safe Clock Monitor (FSCM) .............................. 249 First Start Bit ............................................................ 183 Full-Bridge PWM Output .......................................... 146 Half-Bridge PWM Output ......................................... 145 I2C Bus Data ............................................................ 336 I2C Bus Start/Stop Bits ............................................ 336 I2C Master Mode (Transmission, 7 or 10-bit Address) ......................................... 186 I2C Slave Mode (Transmission, 10-bit Address) ...... 173 I2C Slave Mode (Transmission, 7-bit Address) ........ 171 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ............................. 172 I2C Slave Mode with SEN = 0 (Reception, 7-bit Address) ............................... 170 I2C Slave Mode with SEN = 1 (Reception, 10-bit Address) ............................. 177 I2C Slave Mode with SEN = 1 (Reception, 7-bit Address) ............................... 176 Low-Voltage Detect ................................................. 234 Low-Voltage Detect Characteristics ......................... 322 Master SSP I2C Bus Data ........................................ 338 Master SSP I2C Bus Start/Stop Bits ........................ 338 Parallel Slave Port (PIC18F4X20) ........................... 331 Parallel Slave Port (PSP) Read ............................... 115 Parallel Slave Port (PSP) Write ............................... 115 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 151 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 151 PWM Direction Change ........................................... 148 PWM Direction Change at Near 100% Duty Cycle ............................................. 148 PWM Output ............................................................ 138 Repeat Start Condition ............................................ 184 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ................................. 328 Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) ............. 178 Slave Synchronization ............................................. 161 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 51 SPI Mode (Master Mode) ......................................... 160 SPI Mode (Slave Mode with CKE = 0) ..................... 162 SPI Mode (Slave Mode with CKE = 1) ..................... 162 Stop Condition Receive or Transmit Mode .............. 188 Synchronous Transmission ..................................... 206 Synchronous Transmission (Through TXEN) .......... 207 Time-out Sequence on POR w/ PLL Enabled (MCLR Tied to VDD) ..................... 51 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 1 ....................... 50 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 2 ....................... 50 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 50
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Timer0 and Timer1 External Clock .......................... 329 Transition for Entry to SEC_IDLE Mode .................... 34 Transition for Entry to SEC_RUN Mode .................... 36 Transition for Entry to Sleep Mode ............................ 32 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 247 Transition for Wake from PRI_IDLE Mode ................. 33 Transition for Wake from RC_RUN Mode (RC_RUN to PRI_RUN) ..................................... 35 Transition for Wake from SEC_RUN Mode (HSPLL) ............................................................. 34 Transition for Wake from Sleep (HSPLL) ................... 32 Transition to PRI_IDLE Mode .................................... 33 Transition to RC_IDLE Mode ..................................... 35 Transition to RC_RUN Mode ..................................... 37 USART Synchronous Receive (Master/Slave) .................................................. 340 USART Synchronous Reception (Master Mode, SREN) ...................................... 208 USART SynchronousTransmission (Master/Slave) .................................................. 340 Timing Diagrams and Specifications ................................ 325 A/D Conversion Requirements ................................ 342 Capture/Compare/PWM Requirements ................... 330 CLKO and I/O Requirements ................................... 327 DC Characteristics - Internal RC Accuracy .............. 326 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 332 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 333 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 334 Example SPI Slave Mode Requirements (CKE = 1) ......................................................... 335 External Clock Requirements .................................. 325 I2C Bus Data Requirements (Slave Mode) .............. 337 Master SSP I2C Bus Data Requirements ................ 339 Master SSP I2C Bus Start/Stop Bits Requirements ................................................... 338 Parallel Slave Port Requirements (PIC18F4X20) .... 331 PLL Clock ................................................................. 326 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................ 328 Timer0 and Timer1 External Clock Requirements ................................................... 329 USART Synchronous Receive Requirements ................................................... 340 USART Synchronous Transmission Requirements ................................................... 340 Top-of-Stack Access .......................................................... 54 TRISE Register PSPMODE Bit .......................................................... 109 TSTFSZ ............................................................................ 296 Two-Speed Start-up ................................................. 237, 247 Two-Word Instructions Example Cases .......................................................... 58 TXSTA Register BRGH Bit ................................................................. 198
U
USART ............................................................................. 195 Asynchronous Mode ................................................ 202 Associated Registers, Receive ........................ 205 Associated Registers, Transmit ....................... 203 Receiver .......................................................... 204 Transmitter ...................................................... 202 Baud Rate Generator (BRG) ................................... 198 Associated Registers ....................................... 198 Baud Rate Formula ......................................... 198 Baud Rates, Asynchronous Mode (BRGH = 0, Low Speed) .......................... 199 Baud Rates, Asynchronous Mode (BRGH = 1, High Speed) ......................... 200 Baud Rates, Synchronous Mode (SYNC = 1) .............................................. 201 High Baud Rate Select (BRGH Bit) ................. 198 Operation in Power Managed Mode ................ 198 Sampling .......................................................... 198 Serial Port Enable (SPEN Bit) ................................. 195 Setting Up 9-bit Mode with Address Detect ............. 204 Synchronous Master Mode ...................................... 206 Associated Registers, Reception ..................... 208 Associated Registers, Transmit ....................... 207 Reception ........................................................ 208 Transmission ................................................... 206 Synchronous Slave Mode ........................................ 209 Associated Registers, Receive ........................ 210 Associated Registers, Transmit ....................... 209 Reception ........................................................ 210 Transmission ................................................... 209
V
Voltage Reference Specifications .................................... 321
W
Watchdog Timer (WDT) ............................................237, 245 Associated Registers ............................................... 246 Control Register ....................................................... 245 During Oscillator Failure .......................................... 248 Programming Considerations .................................. 245 WCOL .............................................................................. 183 WCOL Status Flag ............................................ 183, 185, 188 WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 296 XORWF ........................................................................... 297
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NOTES:
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ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2003 Microchip Technology Inc.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39599C FAX: (______) _________ - _________
Device: PIC18F2220/2320/4220/4320 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39599C-page 384
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
PIC18F2220/2320/4220/4320 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. Device
-
X Temperature Range
/XX Package
XXX Pattern
Examples: a) PIC18LF4320-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2220-I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4220-I/P = Industrial temp., PDIP package, normal VDD limits.
Device
PIC18F2220/2320/4220/4320(1), PIC18F2220/2320/4220/4320T(1,2); VDD range 4.2V to 5.5V PIC18LF2220/2320/4220/4320(1), PIC18LF2220/2320/4220/4320T(1,2); VDD range 2.0V to 5.5V
b) c)
Temperature Range Package
I
=
-40C to +85C (Industrial)
Note
1: 2:
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel - SOIC and TQFP packages only.
PT SO SP P ML
= = = = =
TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
2003 Microchip Technology Inc.
DS39599C-page 385
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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ASIA/PACIFIC
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Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
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Dallas
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EUROPE
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Los Angeles
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Phoenix
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China - Shunde
Room 401, Hongjian Building No. 2 Fengxiangnan Road, Ronggui Town Shunde City, Guangdong 528303, China Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
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San Jose
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China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Netherlands
P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
Toronto
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India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
07/28/03
Japan
Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS39599C-page 386
2003 Microchip Technology Inc.

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